Journal of Power Electronics, Vol. 15, No. 4, pp. 951-963, July 2015 951 http://dx.doi.org/10.6113/JPE.2015.15.4.951 ISSN(Print): 1598-2092 / ISSN(Online): 2093-4718 JPE 15-4-9 Manuscript received Oct. 24, 2014; accepted Feb. 26, 2015 Recommended for publication by Associate Editor Lixiang Wei. † Corresponding Author: jagabarsathik@gmail.com Tel: + 91-431-2695606, J. J. College of Engineering and Technology * Dept. of Electrical and Electronics Engg., K. S. Rangasamy College of Technology, India A New Symmetric Cascaded Multilevel Inverter Topology Using Single and Double Source Unit Jagabar Sathik Mohd. Ali † and Ramani Kannan * † Dept. of Electrical and Electronics Engg., J. J. College of Engineering and Technology, Tamil Nadu, India * Dept. of Electrical and Electronics Engg., K. S. Rangasamy College of Technology, Tamil Nadu, India Abstract In this paper, a new symmetric multilevel inverter is proposed. A simple structure for the cascaded multilevel inverter topology is also proposed, which produces a high number of levels with the application of few power electronic devices. The symmetric multilevel inverter can generate 2n+1 levels with a reduced number of power switches. The basic unit is composed of a single and double source unit (SDS-unit). The application of this SDS-unit is for reducing the number of power electronic components like insulated gate bipolar transistors, freewheeling diodes, gate driver circuits, dc voltage sources, and blocked voltages by switches. Various new algorithms are recommended to determine the magnitude of dc sources in a cascaded structure. Furthermore, the proposed topology is optimized for different goals. The proposed cascaded structure is compared with other similar topologies. For verifying the performance of the proposed basic symmetric and cascaded structure, results from a computer-based MATLAB/Simulink simulation and from experimental hardware are also discussed. Key words: Multilevel Inverter, Optimal Structure, Power Conversion, Power Semiconductor Switches, Total Harmonic Distortion (THD) I. INTRODUCTION The multilevel inverter is a kind of dc/ac power converter that produces a desired stepped-like sinusoidal output voltage waveform from an available dc input source [1], [2]. In recent years, this inverter has been widely recommended for medium and high power applications [3]. The important advantages of multilevel inverters are high quality output voltage, low harmonic distortion, low electromagnetic interference, low switching frequency, and low voltage stress on switches [4]. The technical and economic aspects of multilevel inverter development include modular realization, high availability, failure management, investment, and life-cycle cost [5]. Some applications of multilevel inverters include industrial drives, automotive applications, Flexible AC Transmission Systems (FACTS), and traction drive applications [6], [7]. Conventional multilevel inverters are of three types—diode clamped (NPC) [8], flying capacitor (FC) [9], and cascaded H-bridge (CHB) multilevel inverters [10]. The CHB multilevel inverter has received special attention due to its modularity, simple control techniques, reliability, and the absence of capacitor imbalance issues [11]. CHB multilevel inverters are mainly classified into two groups—symmetric and asymmetric multilevel inverters [12]. In symmetric CHB multilevel inverters, the magnitude of all dc voltage sources are equal, requiring an increased number of Insulated Gate Bipolar Transistors (IGBTs) and power diodes, as well as separate dc sources to generate many output levels [13]. These features lead to an increase in installation space and in the total cost of this inverter. In the asymmetric topology, the magnitude of dc voltage sources are unequal. The magnitude of a dc voltage source can be determined using various algorithms. The major advantage of the asymmetric CHB topology is it can considerably increase the number of output voltage levels using few dc voltage sources and IGBTs; however, this topology may also require a variety of dc voltage sources, which is a significant disadvantage. Several novel topologies, along with different new algorithms, for determining the magnitude of dc source voltages have been proposed [14]-[18]. These topologies increase the number of output voltage levels with reduced dc © 2015 KIPE