[Swain, 4(7): July, 2015] ISSN: 2277-9655 (I2OR), Publication Impact Factor: 3.785 http: // www.ijesrt.com © International Journal of Engineering Sciences & Research Technology [440] IJESRT INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY IMPLEMENTATION OF AES ALGORITHM ON MICROBLAZE SOFT PROCESSOR Kaliprasanna Swain * , Manoj Kumar Sahoo, Akash Gaurav *123 Electronics and Communication Engineering, GITA, Bhubaneswar, India ABSTRACT The importance of cryptography applied to security in electronic data transactions has acquired an essential relevance during the last few years. In this work, an FPGA-based implementation of the Advanced Encryption Standard (AES) algorithm is proposed. The proposed design is developed on a soft-microcontroller (Microblaze) using hardware descriptive language (especially Verilog), Xilinx EDK environment. All the results are synthesized and simulated using Xilinx EDK, Xilinx ISE and ISim software respectively. An iterative looping methodology of block and key size of 128 bits is approached and also, S-box lookup table implementation is carried out which gives low latency, low complexity architecture and high throughput. The simulation results show the performance of the design. KEYWORDS: AES, FPGA, encryption, decryption, block cipher, Microblaze, HDL INTRODUCTION In the current scenario, the encryption appears to be an inevitable part of any digital communication system to preserve both transmitted and received information. Encryption is the process by which the original information or text is converted into incomprehensible information commonly known as cipher text by applying a different type of computer algorithm. Among innumerable encryption algorithm, Advance Encryption Standard (AES) is mostly adopted by the U.S. Government Federal department for the safeguard of sensitive information. The specification of this AES is first published in 1997 by the National Institute of Standards and Technology (NIST) [1]. In general, the conventional encryption standards require a single independent key for both transmitting (encryption) and receiving (decryption) [2]. It is impossible to recover the original text from a cipher text without knowing the key. Hence, the security of encryption keys is very much essential. But the software implementation of the encryption key cannot be maintained all the time as the operating system itself prone to hacking. The other pitfalls of the software implementation include CPU design like instruction length, parallelism, mismatch in different operating system, etc. and also, sometime it cannot satisfy the speed required for a particular critical application. Hence, the above disadvantages lead to hardware implementation of the encryption algorithm which can provide more security, more speed and higher efficiency through parallelism. Fig.1 represents the general block diagram of an AES system. Fig. 1: Basic block diagram of AES