International Journal of New Technology and Research (IJNTR) ISSN: 2454-4116, Volume-1, Issue-2, June 2015 Pages 13-15 13 www.alliedjournals.com Abstract—. Conventional LDPC codes have a low decoding complexity but may have high encoding complexity. The encoding complexity is typically of the order O(n2)[5]. Also high storage space may be required to explicitly store the generator matrix. For long block lengths the storage space required would be huge. The above factors make the implementation of the Conventional LDPC codes less attractive. These codes are usually decoded using the sum-product algorithm, which is a message passing algorithm working on the Tanner graph of the code[5]. The sparseness of the parity check matrix is essential for attaining good performance with sum-product decoding. The time complexity of the sum- product algorithm is linear in code length. This property makes it possible to implement a practical decoder for long lengths. Index Terms—LDPC, Cyclic Codes. I. INTRODUCTION Linear codes use a generator matrix G to map a message vector X of length k to a transmitted codeword Y of length n. All codeword satisfy HY=0, where H is the parity check matrix. Gallager defined (n, p, q) LDPC codes to have a block length n and a parity check matrix with exactly p ones per column and q ones per row, where p >=3. The rate of the code is k/n = 1. Gallager proved that, for a fixed p, the error probability of the optimum decoder decreases exponentially for sufficiently low noise and sufficiently long block length. The parity check matrix is typically constructed randomly while constraining the distributions of the row and column vectors as uniform as possible. Since H is not in systematic form, we perform Gaussian elimination using row operations and reordering of columns. II. DECODER ARCHITECTURES The different types of Decoder architecture implementation are Parallel, Serial and Semi- Parallel and are given below[5] Yogita Ahuja , M.Tech Scholar, JNIT University Jaipur Rajsthan Ramesh Bharti, Associate Professor JNIT University Jaipur Rajsthan. A. Parallel Decoder Architecture: A fully parallel implementation of the decoder is shown in figure 2.1. The parallel implementation consists in mapping directly the symbol and check nodes in the Tanner graph to the respective symbol and check modules. The edges of the graph become physical buses of width equal to chosen precision. A fully parallel implementation, while efficient in speed point of view is demanding in terms of area, due to interconnect between the processing elements. Although the computations for calculating the check to symbol and symbol to check messages are not particularly complex and require a small area to be implemented, the massive number of interconnections in the graph lead to complex wiring. In fully parallel architecture the number and complexity of interconnects results in the implementation where almost 60% of the area is being dominated by wires. Moreover, the number of computational blocks required is in one to one relationship with the number of nodes in the Tanner graph. For medium or long code the resource demands and complexity of hardware implementation will become infeasible. Figure 1: Parallel Decoder Architecture B. Serial Decoder Architecture: A serial implementation dramatically reduces the complexity of the interconnect and the total area of the design. The architecture has only one symbol module and one check module so it updates only one message at a time. Even supposing that all computations in the node modules can be executed in one clock cycle, m clocks are needed before the updating r phase is completed, and n clocks before the updating q phase is done. If codes with randomly constructed H matrix are considered, all symbol nodes must be updated Non Binary Low Density Parity Check Codes Decoding Over Galois Field Yogita Ahuja, Ramesh Bharti