POWER OPTIMIZED PLL IMPLEMENTATION IN 180nm CMOS TECHNOLOGY Patri Sreehari Pavankumarsharma Devulapalli Dhananjay Kewale Omkar Asbe KSR Krishna Prasad patri@nitw.ac.in pavan.kumar@nitw.ac.in dhananjaykewale@gmail.com omkarasbe@gmail.com Krish@nitw.ac.in National Institute of Technology, Warangal-506004 ABSTRACT This paper describes the design of power optimized phase locked loop for frequency synthesis, Clock and Data recovery, carrier synchronization and many more communication and VLSI applications. PLL consist of Phase Frequency Detector, charge pump along with passive low pass filter and wide tuning VCO. A modified ring oscillator with tuning range of 280 MHz to 2.47GHz and phase noise of -112.4dBc/Hz at 1MHz offset is designed. Frequency Detector consist of DFF along with CMOS gates with low power architectures. Traditional charge pump, passive low pass filter, modified ring oscillator and divider for frequency synthesis offers less power and system noise. PLL proposed here has lock in range from 500MHz to 1GHz with output frequency ranging from 1GHz to 2GHz, maximum pull in time of 244ns and maximum power consumed is 252μW at 2GHz. Keywords Phase Locked Loop (PLL), Phase Frequency Detector (PFD), Charge Pump (CP), Loop Filter, Voltage Controlled Oscillator (VCO), Pull-in Time 1 INTRODUCTION The Phase frequency detector (PFD) forms the first component of PLL which is designed for high speed application by reducing the dead zone. The architecture of PFD has two D flip flops working in tandem to produce an output signal depending upon phase difference of inputs. Further, charge pump along with passive low pass filter transforms oscillating output of PFD to dc voltage requirement of VCO.VCO decides acquisition range of PLL. The VCO curve has to be monotonic to be employed in PLL. This paper gives PLL system design with operating range of 1GHz to 2GHz which is decided by tuning range of VCO. Generally speaking PLL with high tuning linearity, wide Here we have opted for passive low pass filter which not only reduces system noise but power consumption as well Bandwidth and low noise is preferred and in accordance to application different design architectures are used.VCO and active low pass filter are main noise sources in our PLL. 2 BASIC PLL SYSTEM The basic architecture for PLL.PLL contains PFD, Charge pump, VCO, Loop filter and optional Divider block is shown in Fig.1. 2.1 Phase Frequency Detector The basic function of PFD is to detect the phase or frequency difference between two input frequencies and generate error signal proportional to difference in phase or frequency. . Here we have used the conventional DFF architecture for designing PDF as shown in Fig.2. When reference frequency leads the frequency Fig. 1.Basic PLL Architecture From divider UP signal is generated and vice-versa case generates the DOWN signal of various lengths totally relying on amount of phase variation of input frequencies. CMOS NAND and NOT gate is used in reset circuitry so that if both the input frequencies phases match (UP=1 and DOWN=1) then both FFs are reset to zero. Fig 2. Phase Frequency Detector 2.2 Charge Pump Charge pump converts the UP and DOWN signals generated by PFD into corresponding current values. Charge pump is followed by the loop filter. Charge pump either pumps current into loop filter or pump out the current from loop filter. The circuit of charge pump design along with loop filter is shown in Fig. When UP is high M2 is on and charge pump will pump current in loop filter thus increasing the control voltage, similarly when DOWN is high M3 will be on and current will be drawn out from loop filter and leading to drop of control voltage. Fig 3. Charge Pump 978-1-4799-4006-6/14/$31.00 ©2014 IEEE