High level abstraction method for implementing Image Processing Techniques on FPGA R.Srinivasa Rao, Department of Electronics Engineering, Pondicherry University, Pondicherry, India, srinuindia.123@gmail.com R. Nakkeeran, Department of Electronics Engineering, Pondicherry University, Pondicherry, India, nakkeeran.dee@pondiuni.edu.in Abstract—To implement the image processing techniques on FPGA, line by line Hardware Description Language Programming is time consuming and inefficient. High level abstract hardware oriented parallel programming method can bridge this gap. This paper proposes a method that uses a graphical user interface that combines MATLAB, Simulink and Xilinx System Generator (XSG) and explores important aspects concerned to hardware implementation. In this paper image processing operations like image negative, color to gray scale conversion, image enhancement and image edge detection using XSG on Spartan-3E FPGA are implemented. Keywords — Image Processing, Xilinx System Generator, Simulink, FPGA I. INTRODUCTION AND MOTIVATION The handling of digital images is a subject of widespread interest. Image processing is used to modify pictures to improve them (enhancement, restoration), extract information (analysis, recognition) and change their structure (composition, image editing) [1]. FPGAs are increasingly used in modern imaging applications [2,3] namely image filtering , medical imaging , image compression and wireless communication. The need to process the image in real time, leads to implement them in hardware, which offers parallelism, thus significantly reduces the processing time [4]. The drawback of most of the methods is that they use a high level language for coding, which requires thousands of coding lines for image processing applications which is inefficient as it takes much time. In order to solve this problem, a tool called Xilinx System Generator(XSG) [5-7], with graphical interface under the MATLAB-Simulink [8] is used which makes it very easy to handle with respect to other software for hardware description. The rest of the paper is organized as follows. Section II discusses the requirements for the proposed approach and the different types of blocks used in the design. Section III discusses the basic block diagram of image processing technique. Section IV discusses the design of the various image processing techniques implemented in this paper using Xilinx blocks. Section V discusses the hardware implementation. Section VI discusses the results of all techniques and section VII discusses the conclusion. II. SYSTEM REQUIREMENTS FOR THE PROPOSED APPROACH To design the proposed approach by using XSG a compatible MATLAB and Xilinx ISE software versions required. XSG uses Simulink as the development environment. The entire design uses two kinds of blocks. The blocks in Xilinx System Generator also called ‘Xilinx Blocks’ [5] operate with Boolean values or arbitrary values in fixed point, as they are used to design hardware whereas Simulink blocks [8] works with numbers of double-precision floating point and they are used to give the image in the desired format to the Xilinx blocks. The connection between Xilinx blocks and Simulink blocks are gateway blocks. XSG has an integrated design flow to generate bit stream file directly necessary for programming the FPGA. XSG automatically generates VHDL/Verilog code, a draft of the ISE model being developed and maps hardware, in addition to generating a user constraint file (UCF), simulation, test bench and test vectors among other things . III. SCHEMATIC OF IMAGE PROCESSING TECHNIQUE The entire operation for any image processing technique using Simulink and Xilinx blocks mainly goes through three phases [3] as shown in Fig.1. Fig.1 Basic block diagram A. Image pre processing blocks: As image is two dimensional (2D) arrangement, to meet the hardware requirement the image should be preprocessed and given as one dimensional (1D) vector. The model based design used for image pre processing is shown in Fig.2. To process 2D image it is converted into 1D by using convert 2D to 1D block. Frame conversion block sets output signal to frame based data and provided to unbuffer block which converts this frame to scalar samples at a higher sampling rate. Image pre processing blocks Any image processing technique using xilinx blocks Image post processing blocks IEEE 2nd International Conference on Knowledge Collaboration in Engineering March 27- 28, 2015 978-1-4799-8619-4/15/$31.00 ©2015 IEEE