Performance Analysis of CNTFET Based Digital Logic Circuits Sonal Shreya and Rajeevan Chandel Abstract—Silicon technology continues to scale down and is a dominant choice for high-performance digital circuits. For enhancement of digital circuit performance researchers are further investigating other novel materials to introduce into future technology generations. Carbon nanotubes (CNTs) have been explored as a promising candidate for the same due to their excellent carrier mobility. The effect of CNTFET parametric variation for chirality (or diameter) with threshold voltage on performance metrics namely delay, power and power_delay_product (PDP) has been analyzed in the present paper. It is found that with decrease in diameter of CNTFET, power reduces but with delay penalty. A comparative study of CMOS and CNTFET logic circuits is carried out. An overview of ternary logic is presented. Dependence of threshold voltage on the geometry of carbon nanotube makes it feasible to be used for ternary logic design. Subsequently, circuits in voltage mode ternary logic are implemented using CNTFETs. It is analyzed that CNTFET based circuits are energy efficient. It is also concluded that novel ternary logic is a moderately fast and low power solution to digital circuit design. The circuits have been simulated using HSPICE for 32nm technology node. Keywords—CNT; CNTFET; Chirality; HSPICE; Ternary logic. I. INTRODUCTION Electronic device, technology and circuit researchers are exploring possible alternatives for the future of semiconductor industry to enhance performance of electronic system. Research is being carried out in developing high-mobility transistor channel materials such as III–V compound semiconductors, straining the channel material to improve carrier mobility as well as in using nonplanar transistor structures namely FinFETs and multigate structures. Simultaneously, novel one-dimensional structures e.g., nanowires and carbon nanotubes (CNTs) are also being actively researched. CNTs, with their superior carrier mobility, have emerged as a potential candidate to assist the Si technology roadmap in a post 2015 time frame, although numerous challenges remain [1]. Hence, carbon nanotube field-effect transistors (CNTFETs) provide opportunity for research at both device and circuit levels. This paper briefly describes how carbon nanotube field- effect transistors improve MOSFET performance. Therefore, CNTFETs need to be extensively studied and used as possible successor to silicon MOSFETs [2-4]. The DC characteristics of a CNTFET inherit characteristics similar to those of a MOSFET. Using digital logic circuits like Inverter, NAND, NOR and XOR circuits, a comparative study has been carried out between CMOS and CNTFET technologies in the present work. In order to explore the usage of CNTFET technology parametric variations viz. diameter of CNT, threshold voltage and supply voltage have been investigated in the present work. Digital circuit design has traditionally been associated with binary logic where the two logic levels are represented by two discrete values of current, voltage or charge. However, for the last couple of decades, multiple-valued logic (MVL) has attracted considerable attention, especially among circuit and system designers [5]. MVL circuits allow more than two levels of logic. Depending on the number of allowed levels; ternary base or quaternary base logic styles are developed. MVL circuits can reduce the number of operations necessary to implement a particular mathematical function and thus have an advantage in terms of reduced area. This in turn reduces parasitics associated with routing and provides a higher speed of operation. Further, the overall power dissipation can also be reduced by translating a design from the binary to the ternary or quaternary families [6-11]. It is established in the literature that carbon nanotubes can be configured to have desired threshold voltages depending on their diameters. This has made CNT suitable for voltage-mode ternary logic implementation and has also been explored in the present work. The paper is organized as follows. CNTFET device description and working operation is presented in section II. A comparative analysis of CNTFETs with conventional MOSFET is carried out. Section III demonstrates the design of basic gates using CNTFETs and their performance analyzed. Section III also demonstrates the ternary logic and its implementation on logic circuits. Power, delay and power_delay_product of circuits are the criteria for performance analysis. Conclusions are drawn in section IV. II. CNTFET DEVICE DESCRIPTION Carbon nanotubes are ultra-fine unique devices, which can offer significant advantages over many existing nanostructured materials due to their remarkable mechanical, electronic and chemical properties. A typical device structure of MOSFET like carbon nanotube FET (CNTFET), which consists of drain, gate, source and substrate, is shown in Fig. 1. 978-1-4799-4939-7/14/$31.00 ©2014 IEEE ___________________________________________ Sonal Shreya is PG, VLSI Design student with the Department of Electronics and Communication Engineering, National Institute of Technology, Hamirpur-177005 HP, India (corresponding author phone: +911972-254624; fax: 01972-223834; e-mail: shreya.sonal20@gmail.com). Rajeevan Chandel is Prof. & Head, E&CE Dept., NIT Hamirpur, HP, India (e-mail: rchandel@nith.ac.in).