International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395 -0056 Volume: 02 Issue: 04 | July-2015 www.irjet.net p-ISSN: 2395-0072 © 2015, IRJET.NET- All Rights Reserved Page 190 Test variables selection and multiple parametric faults detection in nonlinear analog circuits G.Puvaneswari 1 , S.UmaMaheswari 2 1 Asst. Prof. (SG), Department of Electronics and Communication Engineering, Coimbatore Institute of Technology, Coimbatore-641 014, Tamil Nadu, India. 2 Associate Professor, Department of Electronics and Communication Engineering, Coimbatore Institute of Technology, Coimbatore-641 014, Tamil Nadu, India. ---------------------------------------------------------------------***--------------------------------------------------------------------- Abstract - A method to select diagnosis variables or test variables for analog circuit testing and to diagnose multiple soft faults in non linear analog circuits using multiple frequency measurements is proposed in this paper. Circuit parameters or the test variables are derived by simulating the circuit under test (CUT) using Modified nodal analysis (MNA) method and are selected based on test vectors. Test vectors associated with each component of CUT are generated with the knowledge of circuit topology and the component values. Testing is performed at multiple frequency measurements to solve the component tolerance challenge in analog circuit testing. The results obtained from simulation of benchmark circuits show the effectiveness of the proposed approach Key Words: analog circuit – fault diagnosis – test vector –tolerance –test variable – multiple frequency- modified nodal analysis 1. INTRODUCTION Analog circuit testing is an important research topic because of non availability of standard procedures or models. The research challenges such as component tolerance, diagnosis variables or test variables, number of diagnosis variables, suitable test frequencies and test nodes selection in analog circuit testing limit the development of standardized approaches for testing. Analog circuit faults are classified as hard faults or catastrophic faults and soft faults or parametric faults. Parametric faults are defined as the variation in component values and hard faults are open or short circuits. Most of the research proposals are for parametric faults detection because parametric faults lead to system performance degradation and are hard to detect. A method based on thresholding approach to detect multiple parametric faults in linear analog circuits is proposed by G.Puvaneswari in [1]. Jian Sun proposed principal component analysis (PCA) and particle swarm optimization (PSO) support vector machine (SVM) based analog circuit fault diagnosis method [2]. To reduce the fault feature dimension principal component analysis and data normalization is used as preprocessing and support vector machine method is used to diagnosis, and particle swarm optimization is used to optimize the penalty parameters and the kernel parameters of SVM, that improve the recognition rate of the fault diagnosis. A slope fault model based fault dictionary approach is proposed by Yang in [3] to select test points and diagnose parametric and hard faults. In [4], Long B introduced a near-optimal feature vector selection method based on Mahalanobis distance for diagnosis of analog circuits using the least squares SVM (LS-SVM). In [1], G.Puaneswari proposed a test vector based multiple fault diagnosis of linear analog circuits. Multiple faults are identified based on the threshold estimated from the fault variables derived for the components of the CUT. A component is said to be faulty if the fault variable is less than the threshold. This paper uses the threshold approach proposed in [1] to detect multiple parametric faults in nonlinear analog circuits and to solve tolerance issue in testing; testing is done at multiple frequency measurements. Test variables selection is done through the test vector values. This paper is organized as follows. Section 2 explains the mathematical background of the paper. Section 3 describes the test flow and section 4 illustrates the