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International Journal of Electronics and Communication Engineering &
Technology (IJECET)
Volume 6, Issue 7, July (2015), pp. 31-37, Article ID: Article ID: 40120150607005
Available online at
http://www.iaeme.com/currentissue.asp?JType=IJECET&VType=6&IType=7
ISSN Print: 0976 – 6464 and ISSN Online: 0976 – 6472
© IAEME Publication
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EXPLOITING DESIGN OF SYNCHRONOUS
COUNTERS METHOD TO DESIGN AND
IMPLEMENT MOD 6 DIRECT DOWN
COUNTER
Bawar A. Abdalla
Department of Software Engineering, Faculty of Engineering,
University of Koya, Koya, Iraq
Zhenar Sh. Faeq
Department of Software Engineering, Faculty of Engineering,
University of Koya, Koya, Iraq
Zrar Kh. Abdul
Department of General Science, University of Charmo, Chamchamal, Iraq
ABSTRACT
In this paper, the design of direct mod 6 down counter is proposed by
using J-K Flip Flop. The counter is provided with synchronous clock pulse.
The counter is implemented by using Electronic Workbench software. The
design can be achieved by the logical function minimization using Karnaugh
map. Vcc and Ground are used for inputs to indicate logic 1 and 0
respectively as well as LED indicators are used to indicate the output bits. The
proposed design is practical to implement any modulus of direct down
counters which can count from any number to zero. This can have advantage
over partial decoding method to design counters which their modulus does not
belong to 2
n
sequence because partial decoding method is only practical for
up counters.
Keywords: Down Counter, Mod 6 Down Counter, Synchronous Counters.
Cite this Article: Bawar A. Abdalla, Zhenar Sh. Faeq and Zrar Kh. Abdul,
Exploiting Design of Synchronous Counters Method To Design and
Implement Mod 6 Direct Down Counter. International Journal of Electronics
and Communication Engineering & Technology, 6(7), 2015, pp. 31-37.
http://www.iaeme.com/currentissue.asp?JType=IJECET&VType=6&IType=7
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