1 Meeting the Design Challenges of nano-CMOS Electronics Campbell Millar * , Scott Roy, David Cummings, Tim Drysdale, Steve Furber, Doug Edwards, Mark Zwolinski, Andy Tyrrell, Alan Murray, Steven Pickles, Richard O. Sinnott, David Berry and Asen Asenov * c.millar@elec.gla.ac.uk, Device Modelling Group, University of Glasgow, www.nanocmos.ac.uk ABSTRACT CMOS transistor scaling has driven the phenome- nal success of the semiconductor industry, delivering faster, cheaper, more functional circuits. 40 nm MOS- FETs are in mass production at the 90 nm technology node, and sub-10 nm transistors will be in production by 2018 (in ultra-thin-body SOI or FinFET form)[1]. However, as devices scale, microscopic variations in their atomically granular structure give rise to macro- scopically measurable variations between devices[2], [3]. Industry now recognises that such variations repre- sent a major challenge to the scaling and integration of current and future nano-CMOS transistors and circuits, and that it will drive revolutionary changes in the way that future integrated circuits and systems are designed. This Glasgow led e-Science Pilot Project, supporting 11 PDRAs and 7 PhD students, combines the top device, circuit, and system design teams in the UK, with industry players in device manufacture, TCAD, analogue & digital fab, and systems design. We aim to show how e-Science technologies can enable a revolution in the electronics design process[4]. Traditional IC design (Figure 1) uses a hierarchical approach that decouples the device, circuit, and sys- tems in order to manage design complexity. Histori- cally (Figure 2) a single device architecture of fixed size required a single compact model set. However, by the 25nm node, in addition to multiple VT devices co-existing on the same chip, bulk devices will be superseded by fully depleted SOI, ultra thin body SOI, and various forms of multi-gate devices including FinFETs. Atomic scale differences in the structure of devices made on these scales cause measurable, ineradicable Figure 1. Traditional decoupled design hierarchy. Figure 2. Multiple device architectures for sub 25nm technology nodes.