International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.3, September 2011 DOI : 10.5121/vlsic.2011.2317 201         Anitha R 1 , Bagyaveereswaran V 2 1 VIT University, Vellore, India. eranitharavi@gmail.com 2 VIT University, Vellore, India. vbagyaveereswaran@vit.ac.in Abstract: The developing an Application Specific Integrated Circuits (ASICs) will cost very high, the circuits should be proved and then it would be optimized before implementation. Multiplication which is the basic building block for several DSP processors, Image processing and many other. The Braun multipliers can easily be implemented using Field Programmable Gate Array (FPGA) devices. This research presented the comparative study of Spartan-3E, Virtex-4, Virtex-5 and Virtex-6 Low Power FPGA devices. The implementation of Braun multipliers and its bypassing techniques is done using Verilog HDL. We are proposing that adder block which we implemented our design (fast addition) and we compared the results of that so that our proposed method is effective when compare to the conventional design. There is the reduction in the resources like delay LUTs, number of slices used. Results are showed and it is verified using the Spartan-3E, Virtex-4 and Virtex-5 devices. The Virtex-5 FPGA has shown the good performance as compared to Spartan-3E and Virtex-4 FPGA devices. Key words: Digital Signal Processing (DSP), Field Programmable Gate Array (FPGA), fast addition, Spartan-3E, truncated multiplier, Verilog HDL, Virtex-4, Virtex-5, Virtex – 6 Low power. 1. INTRODUCTION Multiplication – an important fundamental function in arithmetic operation. Currently implemented in many DSP applications such as FFT, Filtering etc., and usually contribute significantly to time delay and take up a great deal of silicon area in DSP system. Now – a – days time is still an important issue for the determination of the instruction cycle time of the DSP chip. Both the multiplication and the DSP play a vital role in the implementation of VLSI system. Multiplication – Repeated addition of n – bits will give the solution for the multiplication. ie. Multi-operand addition process. The multi – operand addition process needs two n – bit operands. It can be realized in n- cycles of shifting and adding. This can be performed by using parallel or serial methods. This will be simple to implement in two’s complement representation, since they are independent of the signs. It is advantageous to exploit other number systems to improve speed and reduce the chip area and power consumption.