172 • 2014 IEEE International Solid-State Circuits Conference ISSCC 2014 / SESSION 9 / LOW-POWER WIRELESS / 9.8 9.8 An 860μW 2.1-to-2.7GHz All-Digital PLL-Based Frequency Modulator with a DTC-Assisted Snapshot TDC for WPAN (Bluetooth Smart and ZigBee) Applications Vamshi Krishna Chillara 1,2* , Yao-Hong Liu 1 , Bindi Wang 1,2 , Ao Ba 1 , Maja Vidojkovic 1 , Kathleen Philips 1 , Harmke de Groot 1 , Robert Bogdan Staszewski 2 1 Holst Centre/imec, Eindhoven, The Netherlands, 2 Delft University of Technology, Delft, The Netherlands *now at Analog Devices, Limerick, Ireland Ultra-low-power (ULP) transceivers enable short-range networks of autonomous sensor nodes for wireless personal-area-network (WPAN) applications. RF PLLs for frequency synthesis and modulation consume a significant share of the total transceiver power, making sub-mW PLLs key to realize ULP WPAN radios. Compared to analog PLLs [1], all-digital PLLs (ADPLLs) are preferred in nanoscale CMOS as they offer benefits of smaller area, programmability, capability of extensive self-calibrations, and easy portability [2]. However, analog PLLs dominate the field of ULP WPAN radios [1], since the time-to-digital-converter (TDC) of an ADPLL has traditionally been power hungry. We present a 2.1-to-2.7GHz 860μW fractional-N ADPLL in 40nm CMOS for WPAN applications, which breaks the 1mW barrier and consumes at least 5× lower power compared to state-of-the-art ADPLLs. Figure 9.8.1 shows the presented ADPLL architecture with 2-point FM capability. The TX modulation data is added to FCW in the low-frequency path (FM LF ) and the DCO control word in the high-frequency path (FM HF ), allowing the modulation bandwidth to exceed the PLL bandwidth. To meet stringent power constraints, three low-power techniques are employed. The biggest power saving is obtained by using a digital-to-time-converter (DTC)-assisted snapshot TDC for fractional phase detection. It reduces power by ~200× compared to the conventional approach [2]. Secondly, a power-efficient DCO buffer with a tunable voltage- transfer characteristic (VTC) is employed. It is DC-coupled to the low-swing DCO’s output to avoid driving bulky resistor-biased de-coupling capacitors. Finally, a frequency divider (/2) reduces the operation speed of both integer and fractional phase detection to half the DCO rate, CKVD2. This saves power at the expense of doubling the required detection range. A conventional TDC in a counter-based ADPLL [2] needs to cover one full DCO period (T v ) sensing the DCO clock at its full rate, thus consuming several mW. In this work, TDC snapshotting reduces the sampling rate from F CKVD2 to FREF, while the DTC reduces the TDC detection range to less than 1/10 of T v , leading to a significant power reduction. The accumulated fractional part of the frequency command word, FCW frac , controls the DTC to delay the reference signal FREF such that the delayed reference clock FREF dly is almost aligned with CKVD2, once the loop is locked [3]. FREF dly also triggers the snapshot to catch the first CKVD2 edge so that only one CKVD2 edge, CKVD2 S , per reference period is fed to the TDC. A reduced-range TDC operating at the reference frequency (32MHz) then compares the edge of CKVD2 S with FREF dly to provide the fractional phase error, PHE F . Moreover, since the FREF dly and CKVD2 S are synchronized, retimed reference (CKR) is generated by directly sampling FREF dly with CKVD2 S without concerns of metastability [2]. For correct delay prediction, the scaling factor, 1/K DTC (= T CKVD2 /Δt DTC ) is tracked over PVT variations by an LMS-based DTC gain-calibration circuitry that corrects the estimated DTC step by observing the phase error. To generate the integer value of variable phase, PHV, an asynchronous counter clocked by CKVD2 is used as a phase incrementer. Figure 9.8.2 shows the implementation of the DCO, DCO buffer, divider, and phase incrementer/sampler. The DCO is realized by a complementary cross- coupled LC oscillator with digitally tunable tail resistor and capacitors. Using resistors instead of current biasing reduces the flicker noise upconversion. A large inductance (7.7nH) with Q factor of 14 is chosen to minimize the power consumption. The DCO is segmented into three banks: coarse, medium, and fine, to cover a 25% tuning range of 2.1 to 2.7GHz. Switched MOM capacitors, rather than MOS varactors, are used to implement all three banks as they are better modeled, and less sensitive to supply pushing and temperature variations. The resolution of the fine bank, ΔC = ½ C s 2 / (C s + C b ) ≈ ½ C s 2 /C b , is determined by the ratio of capacitors, C b and C s (C b >>C s ). Using a DC-coupled buffer instead of an AC-coupled one, power consumption and noise feed-through into the DCO are reduced. The VTC of the DC-coupled DCO buffer can be varied by digitally controlling the device ratio of PMOS to NMOS (W p /W n ) of the inverter to cover process variation, and is calibrated by monitoring the duty-cycle of the output signal. A transmission-gate-based dynamic divider is used for its high-speed, low-power, and low-voltage operation. Since the divider (/2) reduces the ADPLL operation rate, the phase incrementer can be realized by an asynchronous counter to reduce power consumption. The outputs of the counter are then synchronized by adding appropriate delays before being sampled by CKR to generate the integer part of the variable phase, PHV. Figure 9.8.3 shows the implementation of the DTC/TDC combination. The DTC was adopted in [3] and [4] to replace the power-hungry TDC with a bang-bang phase detector. However, bang-bang ADPLLs either require a complicated frequency detector (e.g., a sampler-based counter in [3]) or warrant additional circuitry for frequency acquisition and loop bandwidth regulation [4], thereby increasing power consumption. In this paper, the DTC is used as a coarse 1 st stage, which assists TDC—a fine 2 nd stage—to reduce the detection range. The DTC with 64 stages covers one CKVD2 period with sufficient margin. A 16-stage TDC covering 1/5 of the CKVD2 period is implemented to avoid long settling time and to help with FM. The digitally controlled delay line in the DTC is similar to the one in [5] except that a cascade of two inverters, instead of one, is used as the delay element to eliminate even-odd mismatches. Moreover, the racing issues are avoided by turning off the preceding inverters when unused. The delay elements are carefully sized for low power consumption while ensuring the mismatch performance meets the fractional-spur requirements in the target applications, i.e. <-30dBc. As shown in Fig. 9.8.3, FREF dly triggers the snapshot circuit to catch the first CKVD2 edge [6]. Compared to the time-windowed architecture [7], this structure is power-efficient as it does not require the full range of the TDC. CKR is generated two CKVD2 periods after the rising edge of FREF dly , to provide enough processing time for the TDC. The TDC is realized by pseudo-differential inverter-based delay lines and sense-amplifier-based flip-flops with identical rising and falling edge metastability windows [2]. The DTC/TDC combination consumes only 43μW. Figure 9.8.7 shows the micrograph of the presented ADPLL, which is imple- mented in TSMC LP 40nm CMOS. It occupies a core active area of 0.2mm 2 . Figure 9.8.4 shows the measured settling behavior, fractional-mode phase noise, and spur level. The PLL settles in 20μs, and has in-band and 1MHz-offset phase noise values of -90 and -109dBc/Hz, respectively. The reference spur is -70dBc, and the worst-case fractional spur for Bluetooth Smart channels is -38dBc. The ADPLL has an rms jitter of 1.71ps (integrated from 1k to 100MHz) and consumes 860μW at 1V supply, leading to a state-of-the-art FoM of -236dB. Figure 9.8.5 shows ZigBee 2Mc/s HS-OQPSK and Bluetooth Smart 1Mb/s GFSK modulation provided by the ADPLL with 2.3% EVM and 5.2% FSK error, while fulfilling all spectrum mask requirements. Figure 9.8.6 shows the comparison of this ADPLL with state-of-the-art low power PLLs. The presented low-power techniques enable ADPLLs to break the 1mW power consumption barrier and thus to be employed in the emerging ULP WPAN applications. References: [1] Y.-H. Liu, et al., “A 2.7nJ/b Multi-Standard 2.3/2.4GHz Polar Transmitter for Wireless Sensor Networks,” ISSCC Dig. Tech. Papers, pp. 448-450, Feb. 2012. [2] B. Staszewski, et al., “All-Digital Phase-Domain TX Frequency Synthesizer for Bluetooth Radios in 0.13μm CMOS,” ISSCC Dig. Tech. Papers, pp. 272–273, Feb. 2004. [3] N. Pavlovic, et al., “A 5.3GHz Digital-to-Time-Converter-Based Fractional-N All-Digital PLL,” ISSCC Dig. Tech. Papers, pp. 54-56, Feb. 2011. [4] D. Tasca, et al., “A 2.9-to-4.0GHz Fractional-N Digital PLL with Bang-Bang Phase Detector and 560fs rms Integrated Jitter at 4.5mW Power,” ISSCC Dig. Tech. Papers, pp. 88-90, Feb. 2011. [5] M. Park, et al., “An Amplitude Resolution Improvement of an RF-DAC Employing Pulse-Width Modulation,” IEEE Trans. Circuits and Systems–I, pp. 2590–2603, Nov. 2011. [6] J. Zhuang, et al., “A Low-Power All-Digital PLL Architecture Based on Phase Prediction,” ICECS’12, pp. 797–800, Seville, Spain, Dec. 2012. [7] T. Tokairin, et al., “A 2.1-to-2.8-GHz Low-Phase-Noise All-Digital Frequency Synthesizer with a Time-Windowed Time-to-Digital Converter,” IEEE J. Solid- State Circuits, pp. 2582-2590, Dec. 2010. 978-1-4799-0920-9/14/$31.00 ©2014 IEEE