International Journal of Applied Engineering Research ISSN 0973-4562 Volume 9, Number 21 (2014) pp. 8889-8900 © Research India Publications http://www.ripublication.com Area and Power Optimized Wallace Tree Multiplier using Power Gating Technique: A Transistor Level Design Anitha R. 1 , S Jakir Hussain 2 , Sarat Kumar Sahoo 3 1 School of Electronics Engineering, ranitha@vit.ac.in 2 School of Electronics Engineering, zakirhussain1218@gmail.com 3 School of Electrical Engineering, sksahoo@vit.ac.in VIT UNIVERSITY Vellore, INDIA\ Abstract In this work we have designed the Wallace tree multiplier at transistor level. In most of the multipliers XOR gate is a key component. The optimization is done at gate level by using the 6T XOR gate instead of conventional CMOS gate. A power gating technique is also used to reduce the leakage power in the design. The simulation was carried out in CADENCE virtuoso with 90nm technology. And the result showed a reduction in area and power of the multiplier. Index Terms— Wallace tree, XOR gate, 6T XOR gate, power gating, 90nm technology, Cadence Introduction The greater emphasis now a day in IC design is performance and miniaturization with reduced power and area. The growing trend towards portable computing and communication systems has made engineers to design systems with reduced area and power. Multiplier is the most important block in most of the digital systems like DSP Processors, microprocessors, etc,. With the advances in technology may researchers have done lot of research to design multipliers with the following specification such as high speed, low power and low area or less delay. However area and speed are inversely proportional to each other i.e. larger the area leads to improving speed. Array multipliers are most commonly used multipliers. The main drawback of the array multiplier is that high power consumption and more digital gates resulting in the increased area of the multiplier. There are various design of the array multiplier. Wallace tree multiplier has been designed with the compressors so as to reduce the latency in [1]. In work carried out in [1] has mainly concentrated on the delay of the