Area Efficient Temporal Coding Schemes for Reducing Crosstalk Effects Jean-Marc Philippe CEA-List DRT/DTSI/SARC/LCEI F-91191 Gif-sur-Yvette Jean-Marc.Philippe@cea.fr S´ ebastien Pillement, Olivier Sentieys IRISA - University of Rennes (ENSSAT) 6, rue de Kerampont 22300 Lannion, France {pillemen, sentieys}@irisa.fr Abstract—In this paper, we present some new crosstalk avoid- ance coding schemes devoted to on-chip busses. These schemes consist in encoding sequences of bits on each line of a bus transferring a packet in order to eliminate worst-case crosstalk patterns. They permit to improve the delay on the link at the cost of doubling the number of transmitted bits. The advantage of the presented solutions is that they have no wiring overhead, so they are independent from the bus bit-width. The coding schemes allow an increase of 50% of the data rate for a 1-mm bus. Moreover, the proposed solutions induce a direction in deep- submicron noise that can be used to implement a noise-tolerant system. I. I NTRODUCTION In modern CMOS technologies, interconnects are the bot- tleneck of high-performance chips. Constraints (such as area or speed) on Systems-on-Chip (SoC) with deep submicron technologies require having high-speed and low area intercon- nects. Due to the increasing density of interconnects, to a lower voltage swing and to an increase of the aspect ratio [1], global on-chip busses suffer from large propagation delay. The main contribution to this delay is due to crosstalk, the interferences due to the coupling capacitance that exists between adjacent wires. The wire capacitances and the dimensions influencing crosstalk are summarized in figure 1. This phenomenon is directly influenced by the coupling capacitances (C c ) between the victim wire V and its two aggressors (A1 and A2). The coupling capacitance between two wires depends on technology constants but also on the dimensions of the wires, such as their length, thickness and the spacing between them. Crosstalk increases the propagation delay on busses. It introduces a delay factor (g), as shown in Table I, where r is the ratio between the cross-coupling capacitance of two adjacent wires (C c ) and the capacitance of a wire to the substrate (C s ) as it is shown by equation 1. r = C c C s (1) In this table, ↑ represents a rising transition, ↓ represents a falling transition and - means that there is no transition on the wire. In the best case, when the three wires are switching in the same direction, the delay on the victim wire is the delay without crosstalk (i.e. g =1), but the bus clock cycle must be adapted exclusively regarding the worst-case delay (i.e. g = 1+4.r) to ensure the integrity of the transmitted data. For a plausible situation where C c = C s , the propagation delay can be multiplied by five or more [2]. Other studies [3] use a parameter r up to 10. Noise induced by crosstalk represents a second issue in deep submicron designs. The coupling capacitance between two adjacent wires introduces a permanent link between them. A transition on a wire affects the two adjacent wires by applying to them a voltage peak [4]. With the technology shrink, crosstalk has a more and more important part in the general noise level. This is due to the increasing coupling capacitance between adjacent wires. As a consequence, the voltage peak induced by cross-coupling is more and more important compared to the voltage swing on a bus line. A1 V A2 L (Length) Cc Cc Cs S (Spacing) T (Thickness) H (Height) Fig. 1. A victim wire and two aggressors. The two wire capacitances are included in this figure. TABLE I EFFECTIVE CAPACITANCE (C eff ) AND DELAY FACTOR (g) OF THE VICTIM WIRE AND THE CORRESPONDING TRANSITION PATTERNS. C eff Transition Patterns g Cs (↑, ↑, ↑) (↓, ↓, ↓) 1 Cs + Cc (-, ↑, ↑) (-, ↓, ↓) (↑, ↑, -) (↓, ↓, -) 1+r Cs +2.Cc (-, ↑, -) (-, ↓, -) 1+2.r (↑, ↑, ↓) (↑, ↓, ↓) (↓, ↑, ↑) (↓, ↓, ↑) Cs +3.Cc (-, ↑, ↓) (-, ↓, ↑) (↑, ↓, -) (↓, ↑, -) 1+3.r Cs +4.Cc (↑, ↓, ↑) (↓, ↑, ↓) 1+4.r This paper introduces some simple coding schemes to avoid worst-case crosstalk patterns. The remainder of the paper is organized as follows. Section II quickly reviews some of the existing crosstalk avoidance techniques. Our approach is explained in section III. We present the experimental results in section IV and we make an analysis of noise issues in section V. Finally, section VI concludes this paper and presents future work. Proceedings of the 7th International Symposium on Quality Electronic Design (ISQED’06) 0-7695-2523-7/06 $20.00 © 2006 IEEE