IJSRD - International Journal for Scientific Research & Development| Vol. 2, Issue 07, 2014 | ISSN (online): 2321-0613 All rights reserved by www.ijsrd.com 684 An Efficient Construction of Online Testable Circuits using Reversible Logic Gates K. Ganesh Kumar 1 R. Arvind 2 S. Gowtham 3 Y. Azain Abdul Kadhar 4 P. Dass 5 1,2,3,4,5 Department of Electronics and Communication Engineering 1,2,3,4,5 Saveetha School of engineering, Saveetha University, Chennai, India Abstract— The vital for many safety critical applications is the testable fault tolerant system. Due to its less heat dissipating characteristics, the reversible logic gaining interest in the recent times. Any Boolean logic function can be implemented using reversible gates. The credential part of the paper proposes a technique to convert any reversible logic gate to a testable gate that is also reversible. The resultant reversible testable gate can detect online any single bit errors that include Single Stuck Faults and Single Event Upsets S. Karp et.al. The proposed technique is illustrated using an example that converts a reversible decoder circuit to an online testable reversible decoder circuit. Key words: Reversible gate, single stuck fault, testable gate. I. INTRODUCTION Reversible Logic has gained importance in the recent past. The rapid decrease in the size of the chips has lead to the exponential increase in the transist account per unit area. As a result, the energy dissipation is becoming a major barrier in the evolving nano-computing era. Reversible logic ensures low energy dissipation. An operation is said to be physically reversible if there is no energy to heat conversion and no change in entropy. In reversible logic, the state of the computational device just prior to an operation is uniquely determined by its state just after the operation. In other words, no information about the computational state can ever be lost and hence the reversible logic can be viewed as a deterministic state machine. Computations performed by the current computers are commonly irreversible, even though the physical devices that execute them are fundamentally reversible. At the basic level, however, matter is governed by classical mechanics and quantum mechanics, which are reversible. With computational device technology rapidly approaching the elementary particle level, it has been argued many times that this effect gains in significance to the extent that efficient operation of future computers requires them to be reversible. Hence, reversible logic is gaining grounds. A reversible gate is a logical cell that has the same number of inputs and outputs. Also, the input and output vectors have a one-to-one mapping. Direct fan-outs from the reversible gate are not permitted. Feedbacks from gate outputs to inputs are not allowed. A reversible gate with n-inputs and n-outputs is called a n x n reversible gate. A previous research has been done on testable reversible circuits. Conditions for a complete test set construction were discussed and the problem of finding a minimum test set was formulated as an integer linear program with binary The technique proposed in this paper can be employed to convert any reversible circuit with arbitrary number of gates to an online testable reversible one and is independent of the type of reversible gate used. The constructed circuit can detect any single bit errors that include single bit stuck-at-fault and single event upset S.Karp et.al . An important advantage of the technique is that the logic design of a reversible circuit remains the same and the reversible circuit need not be redesigned for adding the testability feature to it. Another advantage is that the technique ensures that the garbage generated during the process of conversion to testable reversible circuit is minimized. The proposed technique is illustrated using an example that converts a decoder circuit that is designed by reversible gates to an online testable reversible decoder circuit. II. DESIGN A. Construction of online testable circuit This section describes an algorithmic approach to convert any reversible circuit to an online testable reversible circuit. Given a reversible circuit consisting of reversible gates, the following algorithm converts it into an online testable reversible circuit. Algorithm Input: Reversible Circuit C Output: An online testable reversible circuit C T Construct C' by replacing every reversible gate R in C by TRC(R). The parity input bits of TRC(R) are set such that P ia = P ib in the construction of TRC(R). By Lemma 2, C' is reversible. Fig 1 Fig 1: Block diagram of TRC Let n be the number of reversible gates in C. Construct a (2n+1) x (2n+1) Test Cell (TC) First 2n inputs are the output parity bits from each of the n testable reversible cell TRC of C' gate. The last bit of the input, called e, is either set to logic 0 or logic 1. Fig 2 Block diagram of TC First 2n inputs are transferred to the output without any change. B. Constructible reversible circuit 1) Theorem: The cell TC constructed in Algorithm has the following properties: