A Novel Realization of Reversible LFSR for its Application in Cryptography Prasoon Lata Singh, Alak Majumder, Barnali Chowdhury, Ranvijay Singh, Nikhil Mishra Department of Electronics & Communication Engineering National Institute of Technology, Arunachal Pradesh Yupia, India – 791112 prasoonsingh8@gmail.com , majumder.alak@gmail.com , barnali.cse92@gmail.com , singhranvijay419@gmail.com , nikhilmishra445@gmail.com , Abstract— One-to-one mapping from input to output is the necessary condition for a reversible computational model transiting from one state of abstract machine to another. Probably, the biggest motivation to study reversible technologies is that, it is considered to be the best effective way to enhance the energy efficiency than the conventional models. The research on reversibility has shown greater impact to have enormous applications in emerging technologies such as Quantum Computing, QCA, Nanotechnology and Low Power VLSI. In this paper, we have realized novel reversible architecture of Linear Feedback Shift Register (LFSR) and Parallel Signature Analyzer (PSA) and have explored these in terms of delay, quantum cost and garbage. While approaching for LFSR, we have shown new reversible realization of Serial Input Serial Output (SISO) and Serial Input Parallel Output (SIPO) registers up to N-bit and analyzed their delay, quantum cost & garbage in terms of some lemmas, which will outperform the existing designs available in literature. Keywords– Reversible Logic; SISO; SIPO; Reversible LFSR; Reversible PSA. I. INTRODUCTION The power dissipation of devices is increasing with the technological advancement day-by-day, thereby making it the major limitation of technology. Reversible logic gates due to its ability to reduce power dissipation attracted researcher’s attention. Irreversible gates produce energy loss due to the information bits lost during computation process. Information loss occurs due to less no. of generated output signals than what is applied. According to R. Landauer’s principle[1], given in 1961, irreversible logic gates dissipates KTln2 joules of energy for the loss of 1-bit information, where K is the Boltzmann constant and T is the absolute temperature at which operation is performed which means that the power dissipation is directly proportional to the number of information bit loss. Charles Bennet, in 1973 [2], proposed that, to avoid heat dissipation, logic circuit must be built from reversible circuit since there no information loss occurs. At first, in the design of reversible logic circuits, design was limited to combinational logic circuits and it was just because of the convention that the feedback is not allowed in the reversible computing [19]. But, in 1980, Toffoli [4] has shown that the feedback is allowed in reversible computing. According to Toffoli [11], a sequential network is reversible if its combinational part is reversible. The recent works focus on optimizing the reversible sequential designs in terms of number of reversible gates and garbage outputs. The shift registers are the most exhaustively used functional devices in digital system design for multiple bits storing & shifting of the same if required. In this paper, we are presenting reversible realization of two shift registers naming Serial-in Serial-out and Serial-in Parallel-out for their application in designing sequence pulse generator. We will also present novel reversible architecture of Linear Feedback Shift Register (LFSR) and Parallel Signal Analyzer (PSA). In computing, the input bit of LFSR is a linear function of its last state. The starting value of the LFSR is termed seed, and due to the deterministic operation of the register, the bit stream produced is completely determined by its current (or previous) state. The paper is organized as follows. Section II gives an overview of the related work & the purpose of the work. Section III highlights the basic reversible gates which includes a new MF gate with its quantum representation. Reversible shift register are discussed in section IV with a comparison of them against previous works. Using reversibility, how pulse generation can be done is shown on section V using a particular example. Section VI & VII describes Reversible LFSR & PSA respectively thereby mentioning how they can generate random bit pattern. Conclusion with future scope is discussed on section VIII. II. RELATED WORK The concept of a reversible memory cell was first shown by Fredkin and Toffoli [5], in 1982, where, design of a JK latch was introduced. Later, in 1996, Picton [7] developed a design of clock less SR-latch using two cross- coupled NOR gate, where NOR gates were designed from Fredkin gate. All the reversible latches such as D-Latch, T- Latch etc. along with their flip-flop and master-slave configuration were introduced for the first time in 2005 by Thapliyal et.al.[9]. In 2006, Rice [10] introduced a SR-latch without fan-out problem available in the design by Picton and subsequently designed other latches from SR. In 2007, Thapliyal and Vinod [11] proposed a better design of reversible flip-flops than by Rice in terms of number of reversible gates being used and garbage outputs. A more detailed analysis of SR-latch was presented by Rice [12] in 2008. A better design of all reversible latches (except SR- latch) along with their flip-flops than that of Thapliyal 2015 2nd International Conference on Signal Processing and Integrated Networks (SPIN) 978-1-4799-5991-4/15/$31.00 ©2015 IEEE 601