www.afm-journal.de FULL PAPER © 2012 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim 1209 www.MaterialsViews.com wileyonlinelibrary.com Adv. Funct. Mater. 2012, 22, 1209–1214 Yiheng Qin, Daniël H. Turkenburg,* Ionut Barbu, Wiljan T. T. Smaal, Kris Myny, Wan-Yu Lin, Gerwin H. Gelinck, Paul Heremans, Johan Liu, and Erwin R. Meinders 1. Introduction Thin-film transistors (TFTs), either with organic or inorganic semiconductor materials, have been proposed for various applications in large-area electronics on flexible substrates, for instance, active-matrix displays, [1–3] radio-frequency identifi- cation (RFID) tags, [4] and sensor arrays. [5,6] Several challenges remain in the realization of high-performance TFTs on flexible polymeric substrates. To improve the drive current capacity of organic TFTs (OTFTs), generally characterized by low charge carrier mobilities (below 10 cm 2 V −1 s −1 ), basic device physics commands to use small transistor channel lengths, which is challenging because of the need to form these reproducibly and with perfect alignment between the gate and the source/drain on dimensionally unstable plastic foils, and gate dielectrics with a high dielectric constant (high k), which need to be applicable on plastic substrates at low temperature. Regarding the latter, anodized aluminum (Al) [7,8] has been shown to be a promising dense, uniform, and high-k dielectric layer at low temperature, with good adhesion to the underlying metal and applicable with cost-effective equipment. The current solution to increase the dimensional stability of flex- ible substrates is to temporary bond them on a rigid carrier, called the foil-on-carrier (FOC) approach. [9] A further improve- ment to overcome alignment errors on instable substrates is to use self-aligned patterning, such as self-aligned imprint lithography (SAIL) [10–12] or self-aligned printing [13,14] in which a multi-layer stack of functional layers is patterned in one single imprint step using a multi-level imprint stamp. For a TFT, the source/drain, gate, and gate dielectric geometries are casted in a multi-level stamp and transferred to the substrates via selective etching of a metal-insulator-metal (MIM) stack prepared on the foil. The potential of patterning ultrafine fea- tures [15] makes this technology very attractive for TFT applica- tions. In this study, we present a technology for self-aligned bottom-gate, bottom-contact organic TFTs (OTFTs) on flexible substrates having anodized aluminum oxide (Al 2 O 3 ) gate dielec- tric. The patterning process is realized by one-step, multi-level hot embossing (thermal imprinting) on a large-area, defect-free MIM stack instead of patterning the structures layer by layer with alignment. Such self-aligned embossing process starting from an uniform non-patterned stack allows the use anodized aluminum oxide as a dielectric since the non-patterned gate metal can function as the counter electrode in the anodization process. We demonstrate OTFT channel lengths down to 5 μm and a good electrical performance with high reproducibility. The results are promising in view of large-area production, potentially involving even much smaller structures. 2. Fabrication Processes of Self-Aligned OTFTs Figure 1 is the schematic illustration of the self-aligned embossing patterning process that we developed for manufac- turing bottom-gate, bottom-contact TFTs. Polyethylene naph- thalate (PEN) foil is temporarily bonded to a rigid substrate via a roller laminator. SU-8 photoresist is spin-coated on top of the foil to reduce the surface roughness of polymeric substrate. Subsequently, the MIM stack is deposited onto the prepared FOC substrate. Taking into account the thermal stability of the PEN foil, the gate layer is deposited by sputtering 150 nm Al at Organic Thin-Film Transistors with Anodized Gate Dielectric Patterned by Self-Aligned Embossing on Flexible Substrates An upscalable, self-aligned patterning technique for manufacturing high- performance, flexible organic thin-film transistors is presented. The struc- tures are self-aligned using a single-step, multi-level hot embossing process. In combination with defect-free anodized aluminum oxide as a gate dielec- tric, transistors on foil with channel lengths down to 5 μm are realized with high reproducibility. Resulting on-off ratios of 4 × 10 6 and mobilities as high as 0.5 cm 2 V −1 s −1 are achieved, indicating a stable process with potential to large-area production with even much smaller structures. DOI: 10.1002/adfm.201102266 Y. Qin, D. H. Turkenburg, I. Barbu, W. T. T. Smaal, Dr. G. H. Gelinck, Dr. E. R. Meinders Holst Centre TNO-The Dutch Organization for Applied Scientific Research High Tech Campus 31, 5656 AE Eindhoven, the Netherlands E-mail: daniel.turkenburg@tno.nl K. Myny, W.-Y. Lin, Prof. P. Heremans Imec, Kapeldreef 75, B-3001 Leuven, Belgium Y. Qin, Prof. J. Liu Department of Microtechnology and Chalmers University of Technology Kemivägen 9, SE 412 96 Göteborg, Sweden