Performance Evaluation of Op Amp Using Emerging Device R. Kejariwal, S. C. Bose, A. Islam Dept. of Electronics and Communication Engineering Birla Institute of Technology (Deemed University) Mesra, Ranchi, Jharkhand, India Shruti1115.11@bitmesra.ac.in,Rashmi1114.11@bitmesra.ac.in Abstract— While the selection of new "backbone" device structure in the era of post-planar CMOS is open to a few candidates, FinFET and its variants show great potential in scalability and manufacturability for nanoscale CMOS. In future, as the size of channel length decrease, the necessity of low power based circuit will be increased. In nanometer regime, CMOS based circuits may not be used due to problem in its fundamental material, short channel effect (SCE) and high leakage. To achieve low power device in nanometer region, it can be obtained by utilizing alternative devices like FinFET. This paper analyses an 8T two-stage op amp realized with FinFETs. Its most important design metric that is gain and its variability are analyzed at 32-nm technology node and compared with its CMOS counterpart. This study shows that there is a considerable improvement in feature like gain and its variability due to reduced SCE of FinFET. The FinFET-based op amp emerges out to be better between the two versions of op amp. Findings of our investigation infer that FinFET technology promises to restore the silicon industry by rescuing it from the SCEs that limit device scalability faced by current bulk- CMOS technology. Keywords—FinFET; MOSFET; op amp; gain; variability I. INTRODUCTION From past four decades, device engineers have concentrated on the scaling and performance of device but as per International Technology Road map for Semiconductors (ITRS) [1] suggestion by 2015 gate length of MOSFET will be 10 nm which means that CMOS technology will face significant challenges due to the high channel doping required, band tunneling across the junction and gate induced drain leakage (GIDL), high field effect, lithographic limits and quantum confinement effect. From Moore’s Law, we can infer that FinFET, a nanoscale design [2] represents the most radical shift in semiconductor technology in over 40 years. When Gordon Moore came up with his “law” back in 1965, he had in mind a design of about 50 components [3]. Today’s chips consist of billions of transistors and design teams strive for “better, faster, cheaper” products with every new process node. However, as feature sizes have become finer, the threat of high leakage current due to short-channel effects [4] and varying dopant levels have threatened to derail the industry’s progress to smaller geometrics. This paper realizes a two stage operational amplifier using FinFET and compares its design metrics with its CMOS counterpart. The basic characteristic of FinFET is introduced in section II. Section III represents an overview of op amp using FinFET and MOSFET. The design and performance analysis of the FinFET and MOSFET based op amp are presented in section IV. Section V concludes the paper. This work proposes operational amplifier using FinFET device with reduced variability in its design metrics. To verify the proposed technique, extensive HSPICE simulations using 32 nm PTM (Predictive Technology Model) [5] are carried out. II. STRUCTURE OF FINFET The term FinFET was coined by University of California, Berkeley researchers (Profs. Chenming Hu, Tsu-Jae King- Liu and Jeffrey Bokor) to describe a nonplanar, double-gate transistor built on an SOI substrate [6], based on the earlier DELTA (single-gate) transistor design [7]. The distinguishing characteristic of the FinFET is that the conducting channel is wrapped by a thin silicon "fin", which forms the body of the device as shown in Fig. 1 [8]. The thickness of "fin" (measured in the direction from source to drain) determines the effective channel of the device. The process flow starts the "fin" formation similarly as the formation of active area (in planar CMOS) and followed by STI gap-fill and planarization and oxide recessing to reveal the fins. Then the rest of flow proceeds to similar steps (e.g. well, gate, epi-S/D, etc.) as the planar CMOS with gate-last high-k and metal-gate (HKMG) flow [9]. The working principle of FinFET is similar to that of conventional MOSFET but it has various advantages such as improved SCE and better control over the channel region compared to conventional MOSFET, although FinFET can be fabricated using existing CMOS fabricating facilities.