Memristor-CMOS Hybrid Integrated Circuits for Reconﬁgurable Logic Qiangfei Xia,* ,† Warren Robinett, † Michael W. Cumbie, ‡ Neel Banerjee, ‡ Thomas J. Cardinali, ‡ J. Joshua Yang, † Wei Wu, † Xuema Li, † William M. Tong, ‡ Dmitri B. Strukov, † Gregory S. Snider, † Gilberto Medeiros-Ribeiro, † and R. Stanley Williams † Hewlett-Packard Laboratories, 1501 Page Mill Road, Palo Alto, California 94304, and Technology DeVelopment Organization (TDO), Hewlett-Packard Company, 1000 NE Circle BlVd., CorVallis, Oregon 97330 Received June 11, 2009; Revised Manuscript Received August 20, 2009 ABSTRACT Hybrid reconﬁgurable logic circuits were fabricated by integrating memristor-based crossbars onto a foundry-built CMOS (complementary metal-oxide-semiconductor) platform using nanoimprint lithography, as well as materials and processes that were compatible with the CMOS. Titanium dioxide thin-ﬁlm memristors served as the conﬁguration bits and switches in a data routing network and were connected to gate-level CMOS components that acted as logic elements, in a manner similar to a ﬁeld programmable gate array. We analyzed the chips using a purpose-built testing system, and demonstrated the ability to conﬁgure individual devices, use them to wire up various logic gates and a ﬂip-ﬂop, and then reconﬁgure devices. One possible way to extend Moore’s law 1 beyond the limits of transistor scaling is to obtain the equivalent circuit functionality using fewer devices or components, i.e., get more computing per transistor on a chip. One proposal for achieving this end was the hybrid CMOL (CMOS/molecule) architecture of Strukov and Lihkarev, 2 which was modiﬁed by two of us to improve its manufacturability and separate the routing and computing functions; this was called FPNI (ﬁeld-programmable nanowire interconnect). 3 Rather than relentlessly shrinking transistor sizes, FPNI separates the logic elements from the data routing network by lifting the conﬁguration bits, routing switches, and associated compo- nents out of the CMOS layer and making them a part of the interconnect. Memristor cross bars 4,5 can be fabricated directly above the CMOS circuits, and serve as the recon- ﬁgurable data routing network. A 2D array of vias provides electrical connectivity between the CMOS and the memristor layer. Memristors are ideal for this FPGA-like application because a single device is capable of realizing functions that need several transistors in a CMOS circuit, namely, a conﬁguration-bit ﬂip-ﬂop and associated data-routing mul- tiplexer. A further advantage is that their memory function is nonvolatile, which means they do not require power to refresh their states, even if the power to the chip is turned off completely. 4 Moreover, with appropriate defect-ﬁnding and control circuitry, the redundant data paths of the cross bar structure enable alternate routes through the interconnects, resulting in a highly defect-tolerant circuit. 6,7 Numerical simulations showed that this type of architecture can dramatically increase the logic density of an FPGA-like chip without degrading power dissipation or speed even in the presence of large numbers (up to 20%) of defective com- ponents. 2,3 In this paper, we report the successful implementation of the ﬁrst memristor-CMOS hybrid integrated circuits with demonstrated FPGA-like functionality. The titanium dioxide memristor crossbars were integrated on top of a CMOS substrate using nanoimprint lithography (NIL) 8,9 and pro- cesses that did not disrupt the CMOS circuitry in the substrate. To the best of our knowledge, this is the ﬁrst demonstration of NIL on an active CMOS substrate that was fabricated in a commercial semiconductor fabrication facility. The successful integration shows that memristors and the enabling NIL technology are compatible with a standard logic-type CMOS process. The concept of our memristor-CMOS hybrid circuits is schematically shown in Figure 1a. The memristor crossbar layers (nanowire layer 1, switching layer, and nanowire layer 2) are fabricated on top of a CMOS substrate. There are two sets of tungsten vias coming up from the CMOS, one for the bottom nanowires of the crossbars (red circles in panels a and b of Figure 1) and the other for the top nanowires (blue circles). To make alignment feasible between the * Corresponding author, qiangfei.xia@hp.com. † Hewlett-Packard Laboratories. ‡ Technology Development Organization, Hewlett-Packard Company. NANO LETTERS 2009 Vol. 9, No. 10 3640-3645 10.1021/nl901874j CCC: $40.75  2009 American Chemical Society Published on Web 09/01/2009