Performance evaluation of new scheduling methods for the RR/RR CICQ switch Kenji Yoshigoe a , Ken Christensen b, * , Allen Roginsky c a Department of Computer Science, University of Arkansas at Little Rock, 2801 S. University Ave., Little Rock, AR 72204, USA b Department of Computer Science and Engineering, University of South Florida, 4202 East Fowler Avenue, ENB 118 Tampa, FL 33620, USA c IBM Corporation, Research Triangle Park, NC 27709, USA Received 18 July 2003; revised 13 August 2004; accepted 18 August 2004 Available online 18 September 2004 Abstract Increasing link speeds and port counts in packet switches demand that methods for minimizing internal speed-up and implementing fast scheduling be developed. Combined input and cross point queued (CICQ) switches with round-robin (RR) polling of virtual output queues (VOQ) and of cross point buffers can natively forward variable-length packets without a required internal segmentation into cells. However, native switching of variable-length packets results in unfairness between ports. To eliminate this unfairness, we propose a block transfer mechanism that transfers up to a predefined number of bytes of packet data from a selected VOQ. This mechanism does not require internal speed-up. We also propose an overlapped RR (ORR) arbiter design that fully overlaps RR polling and scheduling. Using simulation and both synthetic and traced packet traffic as input, we show that the RR/RR CICQ switch with the block transfer mechanism has a lower delay than an input queued (IQ) switch that internally uses cells. We also show that the ORR arbiter is scalable, work conserving, and fair. q 2004 Elsevier B.V. All rights reserved. Keywords: Packet switching; CICQ; Variable-length packet 1. Introduction Output queued (OQ) packet switches can achieve 100% throughput for any offered schedulable traffic. OQ switches have buffer memory only at the output ports. Thus, in an OQ switch packets arriving at an input port are immediately transferred to their destination output port. Packets from multiple input ports simultaneously destined for a single output port result in multiple arriving packets to a single output port buffer memory. If packet loss is to be eliminated, OQ buffer memories must operate at N times link speed for N input ports. Due to ever-increasing link speeds and port counts, this N time memory speed-up is not feasible anymore. In input queued (IQ) switches, buffer memories are located at the input ports and these memories need operate only at link speed. Thus, IQ switches offer the best potential for scaling-up to high link speeds and large port counts. A problem with IQ switches is head-of-line (HOL) blocking that results in a maximum throughput of only 58.6% for uniform traffic [15]. Virtual Output Queued (VOQ) switches, first proposed in Ref. [38], resolve HOL blocking by using a switch matrix scheduling algorithm to match input and output ports. Iterative matching algorithms such as PIM [1], iSLIP [22], and FIRM [32] have been introduced for VOQ switches. Iterative matching forces the switch to forward variable-length packets internally in the form of fixed-length cells. This requires the segmentation of packets at the input ports and reassembly of the cells into packets at the output ports. The addition of empty padding bytes is required if a packet is not evenly divisible by a fixed-length cell. Padding bytes are added to the last cell of a segmented packet. The addition of padding bytes requires a speed-up of the switch memories and crossbar. In the worst case, every packet is 1 B larger than the cell size of S, and an internal speed-up of 2S/(SC1) (or almost a factor of two speed-up) is required to maintain switch stability. The buffered crossbar switch was first described in 1988 [2], but the idea at that time was constrained by the size of 0140-3664/$ - see front matter q 2004 Elsevier B.V. All rights reserved. doi:10.1016/j.comcom.2004.08.021 Computer Communications 28 (2005) 417–428 www.elsevier.com/locate/comcom * Corresponding author. Tel.: C1 813 974 4761; fax: C1 813 974 5456. E-mail addresses: kxyoshigoe@ualr.edu (K. Yoshigoe), christen@c- see.usf.edu (K. Christensen), roginsky@us.ibm.com (A. Roginsky).