A Framework for Rapid System-Level Synthesis Targeting to Reconfigurable Platforms A Computer Vision Case Study Dionysios Diamantopoulos, Ioannis Galanis, Kostas Siozios, George Economakos and Dimitrios Soudris School of Electrical and Computer Engineering National Technical University of Athens Athens, Greece 15780 Email: {diamantd, galanis, ksiop, dsoudris}@microlab.ntua.gr Abstract—Reducing time-to-market while improving product quality is a big challenge for system architects of recent multi- million gate System-on-Chips (SoCs). From the software perspec- tive, recent electronics market is governed by the development of hardware-dependent software, i.e. multiple layers of software ready to run optimal on various heterogeneous computing plat- forms from different application domains, such as automotive, consumer and wireless applications. From the hardware perspec- tive there is continuous market trend in configurable systems, so that part of their functionality can be re-programmed to adapt the client’s requirements, i.e. Software Defined Radios (SDRs). In this paper we present a rapid system-level development flow that offers a concurrent fast hardware/software system-level design by enabling a) to start developing, testing and validating the embedded software substantially earlier than it has been possible in the past and b) fast flexible hardware design based on High Level Synthesis (HLS) techniques so that the under- development HW prototype is evaluated and tested in the entire development time. We evaluated our design flow with a computer vision algorithm, i.e. Harris corner detection, and we managed to decrease the development time by almost 64× by pruning the HW design space by 34×, while maintaining designs that trade- off high Quality-of-Report (QoR) on the Pareto frontier. I. I NTRODUCTION With vastly increased complexity and functionality espe- cially in the nanometer era, where hundreds of millions of transistors on one chip are integrated, the design of complex Integrated Circuits (ICs) has become a challenging task. In addition to that, the continuously increased demand for even higher performance (i.e. in terms of operation frequency, power consumption, etc), imposes that new design techniques are absolutely required. Apart from the technology-oriented parameters that affect the efficiency and/or the flexibility of a digital system, the tight time-to-market requirements make conventional ways for product development (e.g. start software development after finalizing hardware) to lead usually in missed market win- dows and revenue opportunities. Hence, there is an absolute requirement for software developers to get an early start on their work, long before the RTL (register-transfer level) of the hardware is finalized. This problem becomes far more important if we take into consideration that software aspects of ICs can account for 80%, or more, of embedded systems development cost [1], making the conventional way for product development insufficient. For instance, the International Technology Roadmap for Semicon- ductors (ITRS) [1] predicts that software development costs will increase, and will reach rough parity with hardware costs, even with the advent of multi-core software development tools [1]. The supporting tools are also crucial for deriving an optimum solution. The existing Electronic Design Automation (EDA) flows are built on the fundamental premise that models are freely interchangeable amongst vendors and have inter- operability amongst them. In other words, this imposes that models can be written, or obtained from other vendors, while it is known a priori that they will be accepted by any vendor tool for performing different steps of physical prototyping (e.g. architecture’s analysis, simulation, synthesis, etc). Even though this concept seems straightforward and promising, it has been proven completely elusive in the world of Electronic System Level (ESL). Specifically, the existing ESL solutions do not provide either model interoperability, or independence between model and software tools. Conse- quently, the adoption of ESL flows between different vendors could be though as a desired feature. Towards this direction, and as research pushes for better programming models for multi-processor and multi-core em- bedded systems, Virtual Platforms (VP) solve one of today’s biggest challenges in physical design: to enable sufficient soft- ware development, debug and validation before the hardware device becomes available. More specifically, with the virtual- ization feature, it is possible to model a hardware platform consisted of different processing cores, memories, peripherals, as well as interconnection schemes, in the form of a simulator [2]. Furthermore, as the task of hardware development progres- sively proceeds, it is feasible to redistribute to software teams updated versions of the VP that enable even better description of target architecture. The concept of virtualization is also important for hardware architects, as it enables easier verification of IP (Intellectual Properties) kernels. This feature could be employed both in the case where only a few of the application’s kernels have to be developed in hardware, as well as if incremental system prototyping is performed. In both cases, the virtualization feature provides all the necessary mechanisms for perform- ing co-simulation and verification between the IPs developed