Digital Control of Resonant Converters: Enhancing Frequency Resolution by Dithering Mor Mordechai Peretz and Sam Ben-Yaakov Power Electronics Laboratory Department of Electrical and Computer Engineering Ben-Gurion University of the Negev P.O. Box 653, Beer-Sheva 84105, ISRAEL. Phone: +972-8-646-1561; Fax: +972-8-647-2949; Emails: morp@ee.bgu.ac.il, sby@ee.bgu.ac.il ; Website: www.ee.bgu.ac.il/~pel Abstract- Resonant converters and related systems, such as piezoelectric transformers, may require a high-resolution frequency drive when the quality factor of the network is high or to avoid limit cycle oscillations. This high frequency resolution requirement could be beyond the capabilities of low cost microcontrollers. To remedy this problem, a frequency resolution enhancement algorithm was developed, tested by simulations and verified experimentally. The proposed approach is based on a modification of the fractional-N dithering concept and includes an adaptive dithering period and smooth DPWM frequency transitions. The implementation of the approach on the digital hardware is simple and requires modest additional workload from the CPU. Theoretical analysis was carried out to model the proposed dithering method when applied to drive resonant network in order to identify the causes and to quantify the expected output signal distortion when the signal is used to drive resonant networks. The proposed approach was tested experimentally on two types of resonant converters: a series-resonant parallel- loaded converter and a piezoelectric transformer. It was found that the output signal distortion is less than 1% of the peak amplitude of the output drive which would be acceptable in many applications. The experimental results were found to be in excellent agreement with the theoretical predictions, validating the usefulness of the dithering method as a frequency resolution enhancer for resonant network drive. I. INTRODUCTION In a variety of applications, variable frequency is the preferred method for output regulation of resonant converter (e.g. fluorescent lamp ballasts piezoelectric devices) [1-3]. In such cases, the frequency resolution of the drive is crucial to ensure accurate operating conditions and the desired load performance. At present, the control of resonant converters is mostly dominated by analog controllers that use Voltage Controlled Oscillator (VCO) with very high resolution capability [4]. In digital controllers, the frequency generation is obtained by timers that can be programmed to reset at a desired value, while maintaining a constant duty ratio of 50%. This is conventionally realized by the embedded Digital PWM (DPWM) of microcontrollers and DSPs peripheral units since they include built-in timers, period compare registers and are capable to operate multiple channels (for synchronous bridge, interleaving etc.) with in-phase, complementary or deadband synchronization. The frequency resolution and accuracy that can be attained by the DPWM units are limited by the system’s clock frequency. Unfortunately, to achieve a performance that is similar to an analog VCO, very high clock frequencies are required that translates into rather costly processors. For example, a 50MHz DPWM clock is needed to generate a 50 KHz signal with frequency resolution of 10bit (50Hz steps). Recent studies related to digital control of resonant converters [5, 6] report the use of either powerful processor with high DPWM clocks to achieve the required control accuracy, or settle for more relaxed specifications that translate into a modest digital hardware [7-9]. Another important aspect of the necessity for high frequency resolution drive, emerges when resonant converters operates in closed loop where the frequency serves as the control signal. In this case, analogous to PWM control design, to avoid limit cycle oscillations of the output at steady state, the frequency resolution of the DPWM has to be made high enough such that the output variation due to a LSB change of the DPWM will be smaller than the ADC resolution levels (one LSB). The conventional method for obtaining a frequency resolution that is higher than what can be achieved by the clock frequency division is frequency dithering. In this approach, the DPWM output frequency is hopped between some values such that the average frequency over time will be in between the DPWM discrete frequencies. The main challenge of this method is that the frequency of the DPWM can be updated only at the beginning of a new count cycle, making this approach impractical in applications that include a low Q resonant tanks which respond fast to frequency changes. The two most popular frequency dithering techniques are the fractional-N and sigma-delta modulation [10-13]. Both methods modulate the DPWM period between two neighboring values, where the frac-N approach operates at a defined rate whereas in sigma-delta the modulation rate changes arbitrarily. It is well documented that the sigma-delta method offers a “cleaner” spectral content of the yielded signal. However, proper operation the sigma-delta modulation requires over- sampling (updating the DPWM during count cycle) which is impractical for smooth signal generation. Furthermore, since frac-N dithering can be simply implemented on the digital 978-1-422-2812-0/09/$25.00 ©2009 IEEE 1202