1 The work described in this paper was carried out with the support of the BONE project (“Building the Future Optical Network in Europe”); a Network of Excellence funded by the European Commission through the 7th ICT-Framework Program. This research has been partially supported by the project CALM TEC2010-21405-C02-02 (subprogram TCM) funded by the Spanish Ministerio de Innovación y Ciencia and and it is also developed in the framework of "Programa de Ayudas a Grupos de Excelencia de la R. de Murcia, F. Séneca". Pablo Pavon Marino, Maria Victoria Bueno Delgado are with Technical University of Cartagena, Plaza Hospital 1, 30202, Cartagena, Spain (phone: +34 968325952; fax: +34 968325973; e-mail: {pablo.pavon, mvictoria.bueno}@upct. Walter Cerroni, Aldo Campi, Franco Callegati are with the University of Bologna, DEIS Department, Via Venezia 52, 47521 Cesena (FC), Italy (phone: +39 0547 339209; fax: +39 0547 339208; e-mail: {walter.cerroni, aldo.campi, franco.callegati}@unibo.it). Abstract—This paper presents PI-OPS (Parallel-Iterative Optical Packet Scheduler) a parallel-iterative scheduler for asynchronous Optical Packet Switching nodes with optical buffering. Optical packets are assembled by aggregating IP packets, and attaching an optical packet header. Conventional schemes process optical packet headers one by one, in a sequential form. Then, worst case algorithm response time is tightly coupled to switch size. In contrast, in PI-OPS all the optical packets received during a given time window are jointly processed to optimize the delay and output wavelength allocation, applying void filling techniques. The scheduler has a deterministic response time, independent of the traffic arrivals pattern. In addition, PI-OPS has been specifically designed to allow a parallel electronic implementation similar to the ones found in VOQ schedulers. In this respect, we evaluate the traffic loss performance of the scheduler in different settings, to dimension a set of hardware related parameters. Finally, we conduct an emulation of an FPGA implementation of a large-scale version of the scheduler. Results support the feasibility of its implementation. Index Terms—Optical Packet Switching, scheduling algorithms, performance evaluation, FPGA prototyping. I. INTRODUCTION dvances in optical communications are considered among the major drivers for the development of future ICT services. In particular, switching paradigms such as Optical Packet Switching (OPS) and Optical Burst Switching (OBS) are able to take advantage of both the huge capacity provided by the photonic technology and the flexibility attainable with a statistical multiplexing approach [1]. Therefore, they are considered attractive candidates for the deployment of next generation network services requiring dynamic provisioning of large amounts of bandwidth on short time scales [2]. Recent studies have also demonstrated the advantages of OBS and asynchronous OPS in terms of reduced CAPEX and power consumption respectively [3][4]. Both OPS and OBS paradigms are based on the use of shared transmission and switching resources, leading to typical packet contention events that cannot be solved using traditional buffering techniques, due to the lack of optical RAMs. In general, contentions could be solved by exploiting three dimensions [1]: the wavelength domain, by using wavelength conversion each time two or more packets need to be simultaneously transmitted on the same fiber; the time domain, by delaying the transmission of some of the contending packets through a finite set of optical delay lines; the space domain, by re-routing some of the contending packets to a different output along a different path to the destination. The combined use of time and wavelength domains proved to be quite effective for both paradigms in terms of logical node performance [5][6]. Several additional contention resolution techniques have been proposed in the literature, especially for the OBS case where significant research effort has been devoted to the burst scheduling problem [2]. However, despite the latest advances in integrated photonics [7] and the significant number of optical switching test-beds available [8], several technological challenges are still to be solved to achieve the feasible deployment of packet-based optical networks. One of these issues is posed by the need for specialized hardware implementing the node control functions. In fact, due to the extremely high packet arrival rates, each node is required to process packet headers in a very short time span to be A parallel iterative scheduler for asynchronous Optical Packet Switching networks P. Pavon-Marino, M. Bueno-Delgado, W. Cerroni, A. Campi, F. Callegati A