Silicon etch process options for micro- and nanotechnology using inductively coupled plasmas C.C. Welch a, * , A.L. Goodyear a , T. Wahlbrink b , M.C. Lemme b , T. Mollenhauer b a Oxford Instruments Plasma Technology, North End, Yatton, Bristol BS49 4AP, UK b Advanced Microelectronic Center Aachen (AMICA), AMO GmbH, Huyskensweg 25, 52074 Aachen, Germany Available online 14 February 2006 Abstract Silicon is an essential material in the fabrication of a continually expanding range of micro- and nano-scale opto-and microelectronic devices. The fabrication of many such devices requires patterning of the silicon but until recently exploitation of the technology has been restricted by the difficulty of forming the ever-smaller features and higher aspect ratios demanded. Plasma etching through a mask layer is a very useful means for fine-dimension patterning of silicon. In this work, several solutions are presented for the micro- and nano-scale etching of silicon using inductively coupled plasmas ICP. Ó 2006 Elsevier B.V. All rights reserved. Keywords: Silicon; Plasma etching; Nanotechnology; ICP 1. Introduction Silicon has to be patterned in the fabrication of a wide range of micro- and nano-scale devices including 2d-pho- tonic crystals [1,2], micro-silicon waveguides [3], nano-sili- con-on-insulator (SOI) MOSFETs [4], grating structures [5] and nanopillar structures [6]. A familiar means of pat- terning silicon is plasma etching by low pressure inductively coupled plasmas (ICP) [7]. This is a high performance tech- nique in wide use for relatively large scale patterning appli- cations such as microelectromechanical system (MEMS) devices. Now there is a need for process strategies to be developed for much smaller feature sizes as required by micro- and nano-scale devices. In this paper three such strategies are described which provide excellent solutions to the challenges of micro- and nano-scale etching of silicon. 2. Experimental Silicon etch process development has been carried out in inductively coupled plasma (ICP) etch equipment from Oxford Instruments. Fig. 1 is a schematic diagram of the Plasmalab System 100 ICP180 as an example. Samples are loaded into the chamber via a load lock and either mechanically or electrostatically clamped to the lower electrode. Helium backside pressure provides good thermal conductance between the electrode and the sample. The electrode temperature may be controlled from À150 to +400 °C. Process gases are admitted to the chamber and controlled to a pressure usually in the range 1–10 mT. Then 13.56 MHz RF power is applied to the ICP coil to generate a high-density etching plasma. 13.56 MHz power is also applied to the lower electrode for independent control of substrate DC bias. Unused feed gas and volatile etch products are pumped away by a backed turbo molecular pump. Silicon etching results were assessed by standard meth- ods: thin film thicknesses by ellipsometry or nanospec, step heights by profilometry and profiles by scanning electron microscopy (SEM). 3. Choice of processes Table 1 summarizes the expected minimum process performance of the three process strategies as used for 0167-9317/$ - see front matter Ó 2006 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2006.01.079 * Corresponding author. Tel.: +44 1934 837000; fax: +44 1934 837001. E-mail address: colin.welch@oxinst.co.uk (C.C. Welch). www.elsevier.com/locate/mee Microelectronic Engineering 83 (2006) 1170–1173