Multi-objective Optimization of a Parameterized VLIW Architecture Giuseppe Ascia Vincenzo Catania Maurizio Palesi Davide Patti University of Catania, Italy Dipartimento di Ingeneria Informatica e delle Telecomunicazioni (DIIT) Viale Andrea Doria 6, 95125 Catania, Italy {gascia,vcatania,mpalesi,dpatti}@diit.unict.it Abstract The use of Application Specific Instruction-set Proces- sors (ASIP) in embedded systems is a solution to the prob- lem of increasing complexity in the functions these systems have to implement. Architectures based on Very Long In- struction Word (VLIW), in particular, have found fertile ground in multimedia electronic appliances thanks to their ability to exploit high degrees of Instruction Level Paral- lelism (ILP) with a reasonable trade-off in complexity and silicon costs. In this case ASIP specialization may require not only manipulation of the instruction-set but also tun- ing of the architectural parameters of the processor and the memory subsystem . Setting the parameters so as to op- timize certain metrics requires the use of efficient Design Space Exploration (DSE) strategies, simulation tools and accurate estimation models operating at a high level of ab- straction. In this paper we present a framework for evalua- tion, in terms of performance, cost and power consumption, of a system based on a parameterized VLIW microprocessor together with the memory hierarchy. Further, the framework implements a number of multi-objective DSE strategies to obtain Pareto-optimal configurations for the system. 1. Introduction The embedded systems market is without doubt the largest and most significant application area for micropro- cessors. There are basically two reasons for its success: the first is the shorter lifecycle for products based on embedded systems, which has led to increased competition between manufacturers, the second is the constant increase in the number, complexity and heterogeneous nature of the func- tions these products have to offer. The reduction in the time-to-market has also made it un- feasible to design a processor from scratch for a specific application. On the other hand, the design of an embed- Compiler Simulator Architecture description Benchmark application Performance numbers Figure 1. The Y-chart approach. ded system is application-specific and so the use of general- purpose microprocessors is often not only inappropriate but also unfeasible in terms of performance, cost, power, etc.. It is widely accepted nowadays that the use of Applica- tion Specific Instruction-set Processors (ASIP) in embed- ded systems provides much more flexible solutions than an approach based on ASICs and is much more efficient than using standard processors in terms of both performance and power consumption [10]. With ASIPs, also known as soft cores, it is possible to modify some of the hardware parameters of the processor to generate a customized in- stance for a specific application domain. To guarantee high performance levels, an ASIP has to exploit the instruction level parallelism (ILP) Architectures based on Very Long Instruction Word (VLIW) processor, in particular, are cur- rently seen as answering the demand for modern, increas- ingly complex embedded multimedia applications, given their capacity to exploit high levels of ILP while main- taining a reasonable trade-off between hardware complexity and cost [14]. Proceedings of the 2004 NASA/DoD Conference on Evolution Hardware (EH’04) 0-7695-2145-2/04 $ 20.00 © 2004 IEEE