1056 IEEE ELECTRON DEVICE LETTERS, VOL. 34, NO. 8, AUGUST 2013 Mechanical Stress Influence on Electronic Transport in Low-k SiOC Dielectric Dual Damascene Capacitor Ya-Liang Yang, Tai-Fa Young, Ting-Chang Chang, Senior Member, IEEE, Jia-Haw Hsu, Tsung-Ming Tsai, Fu-Yen Jian, and Kuan-Chang Chang Abstract— The electronic package with lead-free welding processes must be performed at higher temperature whereas the heat induces to mechanical stress. In this letter, we fabricate a low- k SiOC dielectric comb capacitor with dual damascene (DD) structures to study the mechanical stress influence on leakage current I leak in DD by bending samples. Tensile stress causes increase of the I leak because of the decrease of energy band barrier  of SiOC dielectric. In contrast, compress stress increases  of SiOC and decreases its I leak . Finally, we conclude that the electron transport in DD is dominated by Schottky emission. We found that the variation of I leak is attributed by the change of energy band barrier under mechanical stress. Index Terms— Dielectric, energy band barrier, leakage current, mechanical stress. I. I NTRODUCTION B EYOND 90-nm devices, the process technology is fixed with the low-k SiOC dielectric material and dual dam- ascene (DD) structures with low-resistive Cu (1.67 μ cm) for metal connections [1]. For high-performance logic devices, porous (k > 2.5) and nonporous (k < 3) SiOC materials are the major candidates for Cu/low-k interconnects in advanced nanodevices [2]. In a Pb-free welding process, Sn solder is used for welding chips and printed circuit boards performed at higher temperatures, and thermal and mechanical stresses occur in devices during the cool down in back-end-of-line (BEOL) processes because of different thermal expansions [3]. When thermal and mechanical stresses induce into the chips, which cause device shape bending and leakage current ( I leak ), and become a fail issue. Mechanical bending experiments for stress effect are performed for studying MOS devices [4], but not yet for investigating the influence of the leakage current in low-k SiOC dielectrics. Manuscript received May 27, 2013; revised June 9, 2013; accepted June 14, 2013. Date of publication July 16, 2013; date of current version July 22, 2013. The review of this letter was arranged by Editor S. List. Y.-L. Yang, T.-F. Young, and J.-H. Hsu are with the Department of Mechan- ical and Electro-Mechanical Engineering, National Sun Yat-Sen University, Kaohsiung 80424, Taiwan (e-mail: youngtf@mail.nsysu.edu.tw). T.-C. Chang and F.-Y. Jian are with the Department of Physics, National Sun Yat-Sen University, Kaohsiung 80424, Taiwan. T.-M. Tsai and K.-C. Chang are with the Department of Materials and Optoelectronic Science, National Sun Yat-Sen University, Kaohsiung 80424, Taiwan. Color versions of one or more of the figures in this letter are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/LED.2013.2269831 We have designed a metal-insulator-metal (MIM) capacitor device with DD structure and introduced mechanical stress into the device by bending samples at room temperature to analyze the changes of I leak and further understand the influence of mechanical stress on electronic transport in the SiOC dielectric. It is found that the leakage current density J of the furnace-cured nanoporous silicate film is linearly related to the square root of applied electric field E at 27 °C and 150 °C [5], which corresponds to either Schottky emis- sion (SE) or Pool–Frankel (P–F) emission mechanisms [6]. These two processes can be distinguished by comparing the theoretical values of the energy barrier lowering β and the potential barrier  from calculated slope in the log J versus E 1/2 plot. The current density J SE in SE can be expressed by the following equation [6]: J SE = A ∗ T 2 exp  β SE E 1/2 -  S k B T  (1) where J is the current density, e is the electronic charge, A∗ is effective Richardson constant, T is absolute temperature, β SE is the lowering of Coulombic potential barriers for SE, β SE = (e 3 /4πε 0 ε) 1/2 , ε 0 is the dielectric constant of free space, ε is the high-frequency relative dielectric constant, e is an electron charge, E is the applied electric field,  s is the contact potential barrier, and k B is the Boltzmann constant. For simplification, the external mechanical bending force on sample is evaluated into internal stress using Stoney formula [7] quantitatively. The mechanical stress σ f can be obtained from the following equation: σ f = E s d 2 s 6 R(1 - ν s )d f (2) where σ f is the film stress, E s is Young’s modulus of dielectric, d s is the thickness of sample, R is curvature radius, d f is the thickness of thin film, and ν s is Poisson’s ratio of the thin film of dielectric. An average of Young’s modulus of 101 GPa and Poisson’s ratio ν s = 0.11 are used [8]. II. EXPERIMENTAL SETUP Damascene structured samples with comb capacitors are designed to analyze the leakage current through the stressed low-k dielectric SiOC layer. Comb capacitor devices enlarge parallel metal conducting lines in interconnection. The schematic structure of the device with DD layer structure 0741-3106/$31.00 © 2013 IEEE