Parametric FPGA Early-Late DLL Implementation for a UMTS Receiver B. Cerato L. Colazzo M. Martina A. Molino F. Vacca * CERCOM (Center for Multimedia Radio Communications) Dipartimento di Elettronica, Politecnico di Torino Corso Duca degli Abruzzi 24 - 10129 Torino - Italy Abstract Third generation communication schemes, mainly based on W-CDMA access technique, are replacing the second generation ones both in US and in EU coutries. CDMA makes possible simultaneous communications, spreading the user’s information over a large frequency range by the means of orthogonal codes. One of the main problems of this type of communications is the need for exact alignment between the received sequence and the locally despreading code. The Early-Late block is devoted to maintain this alignment using a Delay Locked Loop, providing that the first alignment will be performed by the synchronizer block. In this paper a reconfigurable Early–Late tracking loop architecture, for SDR implementation, is proposed. Very promising results have been obtained from logical synthesis and from physical implementation on a Xilinx XCV100E (48.7 Mhz, 616 FFs, 719 LUTs). 1 Introduction The wide diffusion of wireless terminals and partic- ularly of cellular phones is opening new challenges in the field of mobile telecommunications. Besides, the possibility to transmit not only voice but even data on a tetherless network, has fostered the development of new technologies and new standards for cellular communications. Software Defined Radio (SDR) is an emerging research topic where the reconfigurability of the receiver architectures is reached by the means of software-based project methodologies [2]. The SDR paradigm can be exploited resorting to different phys- ical layers: in particular it is widely recognized that DSPs and FPGAs are the most suited supports [1]. Besides, when high data rates are involved, FPGAs can better fit the system requirements. A W-CDMA based communication system (i.e. UMTS) can be a * This work has been partially supported by CERCOM (Cen- ter for Multimedia Radio Communications), Politecnico di Torino, ITALY. good case of study of computationally demanding sys- tem. In this paper a parametric Early–Late DLL im- plementation for a CDMA receiver is proposed. Par- ticular care has been posed to the VHDL description in order to make the proposed IP easily reconfigured and tuned to become UMTS compliant. The paper is organized as follows: in section 2 some CDMA principles are described and the main Early– Late DLL characteristics are pointed out. Section 3 deals with the proposed architecture, describing the different functional blocks. In section 4 some experi- mental results are shown and finally in section 5 some conclusions and future works are drawn. 2 CDMA principles CDMA is a technique to access a shared chan- nel resorting to orthogonal codes [5]: the main con- cept is that every user is able to access simultane- ously the channel, spreading its information on a cer- tain band. The band reserved for the communication (B chip ) ought to be wider than the one required by the information itself (B bit ), in order to allow the spread- ing operation. In figure 1 the spreading operation both in the time and frequency domain is depicted, where T bit =1/B bit and T chip =1/B chip . The spreading operation can be accomplished sim- ply multiplying the original signal x n (with band B bit and energy E x ) and the code w n (with band B chip >> B bit ). The resulting signal t n exhibits the same energy of the original one (E x ) spreaded over B chip . If several orthogonal codes are available, more users can access the same channel, provided that each user spreads with a different code. The receiver (fig- ure 2) can recover the information multiplying the re- ceived bitstream against the same code employed by the transmitter for the i-th user. It is important to note how CDMA-based commu- nications exhibit several advantages compared with other channel access techniques. As an example