336 IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS, VOL. 5, NO. 3, SEPTEMBER 2015 Nonlinear Analysis of Discretization Effects in a Digital Current Mode Controlled Boost Converter Amit Kumar Singha, Santanu Kapat, Member, IEEE, Soumitro Banerjee, Fellow, IEEE, and Jayanta Pal Abstract—Digital current mode control finds wide spread application in point of load power converters in DC nano-grid because of its technical benefits. However, finite current-loop sampling effects introduce undesirable sub-harmonic oscillations. This paper presents an analytical framework to investigate such nonlinear phenomena in a digitally current mode controlled boost converter. Discrete-time models for multi-sampled current loops and uniform sample with compensating ramp are derived under continuous conduction mode. We show that the discrete-time maps for such systems are discontinuous in nature. While the error voltage using a proportional-integral controller stays within the zero-error-bin (ZEB), the reference current becomes constant and 1-D maps of the inner current-loop can be used for stability analysis. Uniform sampling may lead to chaos, period doubling or stable period-1 behavior depending on slope of the compensating ramp. Multi-sampled current loop imposes several borders in the discrete parameter space and may eventually lead to high periodic behavior. In a counter-based compensating ramp, staircase effects may lead to sub-harmonic oscillation. Such instability eventually brings the error voltage outside the ZEB and 2-D map models have to be used for further investigating the nonlinear phenomena. A boost converter prototype was made. Digital current mode control is realized using an FPGA device. Test results demonstrate close agreement with the analysis. Index Terms—Boost converter, digital current mode control, dis- continuous maps, discrete-time maps, nonsmooth bifurcation. I. INTRODUCTION D IGITAL current mode control finds widespread applica- tion in point of load power converters in DC nano-grid because of its technical benefits, such as the feasibility of imple- menting advanced control techniques [1], [2]. However, sam- pling and quantization effects additionally introduce various un- desirable nonlinear phenomena. These nonlinear effects may lead to instabilities, and EMI problems [3]. This paper addresses some of these issues in a digitally current mode controlled boost converter from a theoretical perspective. Manuscript received 5 March 2015; revised 30 April 2015; accepted May 27, 2015. Date of publication August 11, 2015; date of current version September 09, 2015. This work was carried out at the Embedded Power Management Lab., Department of Electrical Engineering, IIT Kharagpur-721302, India. This paper was recommended by Guest Editor D. Giaouris. A. K. Singha and S. Kapat are with the Department of Electrical Engineering, Indian Institute of Technology (IIT), Kharagpur, India (e-mail: amitkumar@ee. iitkgp.ernet.in; santanu.kapat@ieee.org). J. Pal is with the School of Electrical Sciences, IIT Bhubaneswar, Bhubaneswar, India (e-mail: jayanta.j05@gmail.com). S. Banerjee is with the Indian Institute of Science Education and Research, Kolkata, India (e-mail: soumitro@iiserkol.ac.in). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/JETCAS.2015.2462151 Peak current mode control (CMC) offers several perfor- mance benefits over voltage mode control (VMC) in DC-DC converters, such as improved closed-loop bandwidth and sta- bility margin, excellent line regulation, etc., [4], [5]. Further, online controller reconfiguration makes digital current mode control an attractive choice in mainstream power electronics. Since the inductor current in a PWM DC-DC converter varies fast, a high frequency digital CMC (DCMC) implementation would require high speed analog-to-digital (A/D) converters, particularly for sampling the current loop. This would increase hardware complexity, cost, and power consumption. Over the last decade, significant research efforts were made to develop simple yet effective DCMC techniques [6]–[13]. The predictive CMC in [6] considers uniform current loop sam- pling and predicts the inductor current using the information of system parameters. A uniformly sampled DCMC in [7] con- siders a virtual ramp compensation throughout. A mixed-signal current mode control was developed in [8], in which the voltage controller utilizes digital implementation and the current loop remains in the analog domain. Sensorless digital current mode control was developed in [9]. Due to slower output voltage dynamics and smaller ripple in digital VMC, quantization effects are more pronounced than the effects of finite sampling, which may lead to limit cycle oscillations [14]–[18]. However, the effects of finite current-loop sampling are expected to be significant in digital CMC because of fast changing inductor current with considerable ripple magnitude. Past research on the nonlinear phenomena in power elec- tronic systems has demonstrated the occurrence of subharmonic oscillation, quasi-periodicity, and chaos when the parameters vary beyond certain limits. But these studies are mainly limited to analog controllers [19]–[25]. Existence of limit cycle oscil- lations in digitally current-mode controlled DC-DC converters was reported in [7]; however, DCMC exhibits more complex nonlinear phenomena. An open-loop DCMC architecture was recently proposed to overcome sub-harmonic instability via real-time duty ratio computation [26]. However, it still remains unexplored to investigate underlying nonlinear phenomena in DCMC using a unified framework. In this paper, a prototype of digital current mode controlled boost converter is implemented and the effect of sampling in in- ductor current is demonstrated using time domain waveforms. We then derive discrete-time models as a tool to analyze the ob- served effects. When the slow varying dynamics of the outer voltage loop is ignored, the discrete time model takes the form of a one-dimensional discontinuous map, which is easy to an- alyze. We show that finite current loop sampling imposes sev- eral borders in the discrete parameter space and border collision 2156-3357 © 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. 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