Graph Covering for generating instruction specific application instructions: an overview of some existing methods Carlo Galuzzi Koen Bertels Stamatis Vassiliadis Computer Engineering, EEMCS Delft University of Technology {carlo, k.l.m.bertels, s.vassiliadis}@ewi.tudelft.nl Abstract The execution time of an application can be consid- erably reduced by implementing parts of the applica- tion in hardware instead of software. Graph Theory can be used for selecting which parts of the application are suitable for an hardware implementation. To this purpose, the application is represented as a directed graph, called a subject graph, and the selection prob- lem can then be described as the search and selection of subgraphs having particular properties. The subgraph identification problem requires the evaluation of two separate issues: a coverage problem of the subject graph and a selection problem of the subgraphs. The complexity of the problems involved has led researchers to provide both exact solutions as well as heuristic solutions representing a trade-off between the goodness of the solution provided and the resources used to obtain it. Although a heuristic solution is usually used to limit the search space, how much is left uncovered is what influences the goodness of the solution. This depends on the parameters that are taken in consideration to evaluate the solution as area, delay, etc. In this paper we provide an overview of the main is- sues related to the coverage of the search space point- ing out the goodness of the solutions provided as well as the main features of the method applied to obtain it. Keywords Covering problem, Subgraph identification, Graph Theory. I. Introduction Our life is more and more surrounded by electronic devices that everyday become smaller and increase the number of tasks they can perform. Although in the past years ASICs and GPPs were the main ways adopted to implement the functionalities of these de- vices, over the last years their use has seen a progres- sive shift toward the use of reconfigurable architec- tures ([27], [29], [20]) which are gaining ground day by day and are progressively replacing them in many cases. These architectures have the property to be re- configurable totally or partially and this allows them to be used not only for the original task but for new tasks as well, avoiding the design-process of a com- plete new device and reducing costs. An example of reconfigurable architecture can be realized combining a GPP with a reconfigurable part as an FPGA ([1]). When a program is executed on this architecture, a certain number of instructions are hardwired whereas the rest of the operations are im- plemented by software. The reconfigurable part can then be used to hardwire some instructions of those implemented by software. It doesn’t exist basic pro- cedure to share out the instructions among hardware and software; what exists it’s a huge number of differ- ent types of approaches guided by different prospects and constraints. Although the final goals are often dif- ferent and constitute a huge variety, all the approaches follow a common guideline. Goal of this paper is to present this guideline showing how this selection can be done and which are the metrics involved in this choice. The shift of one instruction from software to hard- ware can reduce some metrics like the execution time, and then a right balance between hardware and soft- ware can improve and maximize performance. This balance, often addressed as hardware/software parti- tioning problem or hardware/software codesign prob- lem ([6], [25]), it is an interesting problem whose so- lution is frequently branched out into many different fields ranging from graph theory to selection prob- lems. The complexity of the problem, how we see NP ([28]), has an influence on the solution which most of