Low-temperature LPCVD of Si nanocrystals from disilane and trisilane (Silcore®) embedded in ALD-alumina for non-volatile memory devices I. Brunets ⁎ , A.A.I. Aarnink, A. Boogaard, A.Y. Kovalgin, R.A.M. Wolters, J. Holleman, J. Schmitz MESA + Institute for Nanotechnology, Chair of Semiconductor Components, University of Twente, P.O. Box 217, 7500 AE Enschede, The Netherlands Available online 30 March 2007 Abstract Non-volatile memory devices are realized using CVD and ALD of all active layers in a cluster tool. The floating gate consists of silicon nanocrystals. A high nanocrystal density was obtained through an enhanced nucleation rate by using disilane (Si 2 H 6 ) as well as trisilane (Si 3 H 8 , known as Silcore®) as precursors for low-pressure chemical vapor deposition (instead of silane). The deposition temperature was 300–325 °C and the deposition pressure ranged between 0.1 and 10 mbar. To prevent oxidation of the nanocrystals, they were encapsulated directly after deposition with a 10-nm thick ALD-grown Al 2 O 3 layer (blocking oxide). The deposition of Si-nanocrystals as a function of substrate temperature, precursor flow rate and total gas pressure was explored. Appreciable retention and endurance were measured on realized Al/TiN/Al 2 O 3 /Si-nanocrystal/SiO 2 / Si(100) floating-gate capacitor structures. © 2007 Elsevier B.V. All rights reserved. Keywords: LPCVD; ALD; Nanocrystal; Non-volatile memory; Silicon; Trisilane; Thin film 1. Introduction The constantly growing market of portable electronic de- vices (e.g., mobile phones, digital cameras, data storage devices, notebooks) demands low-cost, high-density, and highly-reliable memories (such as SRAM, DRAM, EPROM, EEPROM and flash memories). Flash memory downsizing is reaching its phys- ical barriers, and several new devices are presently investigated as replacements for the traditional floating-gate stack; one of which being the nanocrystal memory cell [1–4]. In the mean time, IC manufacturing drives towards lower thermal budgets, and aims at 3-D integration [5,6]. In this paper, we investigate an approach to fabricate silicon- nanocrystal memory cells with a low thermal budget (well below 400 °C). The advantage of the discontinuous nanocrystal floating gate over continuous floating gates is that charge state is much less dependent on local leaks in the gate oxide (see Fig. 1a). This allows the use of CVD gate oxides with a higher density of weak spots compared to thermally grown oxide. A CVD reactor cluster, combining ALD of metal oxides, metal nitrides, and an ICP- plasma deposition reaction chamber, was custom-built to investigate low-temperature deposition processes. With this reactor, all essential deposition steps for device realization can be combined at low temperature and without vacuum break. Such depositions are here carried out on (100) silicon wafers, but may lead to suitable memory devices also on re-crystallized amorphous-silicon layers (see e.g. [7]), opening the way to 3-D memory structures inside the microchip's backend. 2. Experimental In this work, the functional multilayer Al/TiN/Al 2 O 3 /Si- nanocrystal/SiO 2 /Si stack was realized. Two different materials were chosen for the tunnel and blocking gate dielectrics (i.e. silicon dioxide with k = 3.9 and alumina with k = 9, respective- ly), providing a higher electric field across tunnel oxide. Thus, the Fowler–Nordheim tunneling mechanism could be applied for charging and discharging the Si-nanocrystals [8]. 2.1. Cluster system design The functional layer stack with embedded silicon-nanocrys- tals was realized in our cluster system consisting of three single- Surface & Coatings Technology 201 (2007) 9209 – 9214 www.elsevier.com/locate/surfcoat ⁎ Corresponding author. Tel.: +31 53 489 4394; fax: +31 53 489 1034. E-mail address: i.brunets@utwente.nl (I. Brunets). 0257-8972/$ - see front matter © 2007 Elsevier B.V. All rights reserved. doi:10.1016/j.surfcoat.2007.03.035