Amorphous-fcc transition in Ge 2 Sb 2 Te 5 S. Lombardo a, * , E. Rimini b , M.G. Grimaldi b , S. Privitera c a CNR-IMM, Stradale Primosole 50, 95121 Catania, Italy b Dipartimento di Fisica e Astronomia, Università di Catania, Via S. Sofia, 64, I-95123 Catania, Italy c STMicroelectronics, Stradale Primosole 50, 95121 Catania, Italy article info Article history: Received 14 April 2009 Received in revised form 16 July 2009 Accepted 7 September 2009 Available online 12 September 2009 Keywords: Phase change memories Chalcogenides GST Phase transitions abstract In this paper we discuss some major aspects on the physics of the phase transition from the amorphous to the face-centered-cubic (fcc) polycrystal in Ge 2 Sb 2 Te 5 at low temperature. We follow the phase transfor- mation by using structural techniques such as TEM, XRD, and electrical resistivity measurements by using the 4-point-probe technique. The results are interpreted in the framework of a quantitative model. Ó 2009 Elsevier B.V. All rights reserved. 1. Introduction Phase change memories (PCMs) are a very promising novel concept for the realization of semiconductor non volatile memo- ries, both for stand-alone and embedded applications. The basic operation principle is the first order phase transition in chalcoge- nides alloys between the amorphous low conductivity phase and the high conductivity polycrystal. In particular the Ge–Sb–Te alloys belonging to the pseudobinary line joining GeTe to Sb 2 Te 3 are particularly attractive since rapid and reversible changes between the disordered and ordered atomic structure can be made with no phase separation. Going towards the GeTe rich compositions the melting and crystallization temperatures monotonically increase [1], and probably the best compromise between data retention and crystallization/amorphization speed is the Ge 2 Sb 2 Te 5 (GST), the most widely investigated stoichiometry for the application to PCMs. In particular it is exploited the amorphous/polycrystalline phase centered cubic (fcc) structure transformation, which is a reversible first order phase transition between metastable phases [2–4]. The peculiar characteristic that renders GST attractive as storage medium is the co-existence of a large activation energy for crystallization (around 2.5 eV), coupled with relatively low transition temperatures. Other important features are the low melting temperature, around 620 °C, and the low thermal conduc- tivity, which favors localized heating. The PCM cells consist in a GST resistor in series with an address transistor, and they are realized by using two major categories of design, horizontal [5,6] and vertical [7]. In both cases the trans- formed GST volume has a small radius, of the order of a few tens of nm. The write/erase mechanisms are obtained by applying fast electrical pulses to the GST resistor and involve a number of impor- tant basic aspects. First, the amorphous-to-crystal transition (set operation) requires the threshold switching, i.e. a sudden increase of the amorphous conductivity as the bias applied to the GST resis- tor reaches a threshold voltage. The high conductivity is crucial in order to initiate a large current pulse and electrical power dissipa- tion which triggers the crystallization of the amorphous by Joule heating. The threshold switching in amorphous GST is attributed to an interplay between carrier avalanche and charge recombina- tion through defects [8,9]. The reverse transition to the amorphous (reset) is obtained by a large and rapid current pulse [10] which produces melting followed by a rapid quenching. Set and reset cur- rents scale very rapidly as device size decreases [11], and reset pulses as low as 90 lA have been demonstrated [6]. The very low operation voltages, fast set/reset mechanisms, the very low cost are extremely attractive properties as replacement to standard floating gate non volatile memories. However, PCMs present two major drawbacks which need further development. One limits the application of PCM as multi-level memory, and it is the drift effect of the amorphous phase resistance, i.e. a resistance increase occurring at low temperatures, even at room temperature, attributed to defect annealing [12]. The second major issue is due to the low temperature crystallization of the amorphous phase [13], which may limit the data retention under operation conditions and therefore the reliability of PCMs. 0167-9317/$ - see front matter Ó 2009 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2009.09.005 * Corresponding author. Present address: IMS R&D, STMicroelectronics, Catania, Italy. Tel.: +39 095 5968223; fax: +39 095 5968312. E-mail address: salvatore.lombardo@imm.cnr.it (S. Lombardo). Microelectronic Engineering 87 (2010) 294–300 Contents lists available at ScienceDirect Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee