 Tier 1 : CMOS SoC  TSV  Very thin wafer  Interface u-Bump  Backside metal  Interface to u-Bump  TSV/u-Bump offset  U-Bump  Very thin underfill  Tier 2 : Memory/Analog  Regular die  Frontside metal  Package Bump  Regular flip chip bump  Regular underfill  Package  Regular substrate  Regular plastic potting Tier 1 Die ~ 10’s um TSV Size ~ 1’s um Pitch ~ 10’s um Tier 1 FEOL ~ 1’s um Back Metal Width ~ 1’s um Pitch ~ 10’s um u-Bump Size ~ 10’s um Pitch ~ 10’s um Underfill ~ low 10’s um Tier 2 Die ~ 100’s um Tier 2 FEOL ~ 1’s um Package Bump Size ~ 100’s um Pitch ~ 100’s um Package Substrate ~ 100’s um Underfill ~ hi 10’s um ~mm Fig. 1 Schematic of the 3D TSV chip stacking architecture. Simulation Methodology and Flow Integration for 3D IC Stress Management Mark Nakamoto 1 , Riko Radojcic 1 , Wei Zhao 1 , Vinay K. Dasarapu 2 , Aditya P. Karmarkar 2 and Xiaopeng Xu 3 1 Qualcomm, Inc., San Diego, CA, USA 2 Synopsys (India) Private Limited, Hyderabad, Andhra Pradesh, India 3 Synopsys, Inc., Mountain View, CA, USA Abstract—a new methodology to bridge package and silicon domain simulations is demonstrated using a new data file to facilitate stress information exchange. The flow integration uses equivalent stress conditions to replace sensitive process information and parameterized modules to minimize user interventions for 3D IC stress simulations. Keywords— Through-silicon via (TSV), mechanical stress, layout proximity, performance variation, reliability, modeling I. INTRODUCTION Three dimensional (3D) integration technologies use through silicon vias (TSVs) to link silicon dies that are encapsulated in a package, as shown in Fig. 1. New processes for 3D IC integration introduce mechanical stresses not only in silicon active regions but also in interconnect and package structures[1][2]. Mechanical Stress modulates the transistor performance and also compromises the structural integrity and reliability. These concerns are not addressed in the existing modeling methodologies and design flows. Currently mechanical stress is managed independently in the silicon and package domains. The lack of a methodology that bridges silicon and package domains imposes a severe constraint for 3D IC stress management. For silicon domain stress analysis, designers face additional modeling constraints, since conventional TCAD simulation requires detailed process information not accessible to fab-less companies. Apart from these constraints, the complex 3D multi-disciplinary nature of the problem requires robust and easy to use simulation methodology. In this paper, innovative techniques are employed to overcome these constraints and a modeling framework is developed for 3D TSV stress analysis with parameterized geometry and mesh generation modules. II. BRIDGING PACKAGING AND SILICON Traditionally mechanical stress modeling for packaging and silicon has been performed as two distinct functions, and often by different organizations. Package modeling is typically focused on reliability issues such as solder ball fatigue, die cracking and more recently de-lamination or cracking of ultra low- dielectric layers on the die. On the other hand, silicon mechanical simulation is most often focused on performance enhancement or degradation at the single transistor level. Strained silicon methods have played a major role in recent generations of CMOS technology. The advent of 3D integration has significantly increased the level of interaction between the silicon and the packaging domains. Existing features and factors such as soft low- dielectrics, strained silicon and CTE mismatch with packaging material will now interact with new 3D features and processes. Dies thinned to 10s of m will be much more susceptible to bending or warpage due to the normal BEOL film stack and packaging stresses. These will also interact with new features such as TSVs, -bumps and other dies in the 3D stack [4]. One example is a -bump connection between two dies that would normally be simulated in the package modeling realm as shown in Fig. 2 (a); where the force is usually not high enough to cause reliability concerns. However, when the mechanical stress from this “packaging” effect is transferred to the silicon simulation domain, the impact of stress on the silicon performance is evident from the mobility change shown in Fig. 2 (b). Accordingly, there is an increasing demand for accurately modeling stress induced transistor performance deviation at the silicon die level, while accounting for both global and local stress sources and their interactions. This requires a hierarchy of sub-modeling from global packaging level to local silicon level. However, the nature of packaging level modeling can be different from that of silicon level modeling. For example, the packaging level modeling often involves 978-1-4244-5760-1/10/$26.00 ©2010 IEEE