Thermo-uid analysis of micro pin-n array cooling congurations for high heat uxes with a hot spot Abas Abdoli, Gianni Jimenez, George S. Dulikravich * Florida International University, Department of Mechanical and Materials Engineering, MAIDROC Laboratory, Miami, FL 33174, USA article info Article history: Received 23 July 2014 Received in revised form 22 December 2014 Accepted 22 December 2014 Available online Keywords: Electronics cooling Micro pin-n High heat ux chip Hot spot Conjugate heat transfer abstract Effect of micro pin-n shapes on cooling of high heat ux electronic chips with a single hot spot was investigated numerically. Hydrothermal performances of different micro pin-n shapes were evaluated. Circular shape, hydrofoil shape, modied hydrofoil shape, and symmetric convex shape were the cross section shapes used for micro pin-ns. All cooling congurations had the same staggered arrangements for micro pin-ns. An electronic chip with a 2.45 2.45 mm footprint having a hot spot of 0.5 0.5 mm at its centre was used for simulations. Uniform heat ux of 2000 W cm 2 was applied at the hot spot. The rest of the chip was exposed to 1000 W cm 2 uniform heat load. The cross section area of the circular shape and hydrofoil shape micro pin-ns was kept the same to have a fair comparison. Convex and hydrofoil shape designs showed signicant reduction in the required pumping power as well as the maximum required pressure. In the last case, the height of micro pin-ns was increased from 200 mm to 400 mm to remove 100% of the total heat load via convection, and at the same time keep the maximum temperatures within an acceptable range. © 2014 Elsevier Masson SAS. All rights reserved. 1. Introduction Three-dimensional (3-D) integrated circuits (ICs) are believed to be the best way to overcome barriers in inter-connect scaling and keep Moore's law ticking by providing an opportunity for continued higher performance ICs in the semiconductor industry [1]. Smaller size, higher performance, better functionality and lower consumption of power are some of the major advantages of 3-D ICs. On the other hand, increasing demand for removing heat from 3-D ICs has become the major challenge in this eld and has constrained their applications. The next generation of the elec- tronic chips is expected to produce heat uxes up to 500 W cm 2 as the background and more than 1000 W cm 2 at hot spots [2,3]. Sahu et al. [4] applied a hybrid cooling scheme which combines microuidic and solid-state cooling techniques in cooling hot spots with the heat ux close to 250 W cm 2 . In other research, Sahu et al. [5] studied a liquid-thermoelectric hybrid cooling method for hot spots having heat uxes of more than 600 W cm 2 . They reported that liquid-thermoelectric hybrid cooling showed better results for higher heat uxes at hot spots. Abdoli and Dulikravich [6] performed multiobjective optimization for multi-layer straight and branching counterow microchannel congurations with 67 design variables to maximize heat removal capacity, while mini- mizing temperature non-uniformity and coolant pumping pressure drop. They also optimized the multi-layer through-ow micro- channels for heat uxes up to 1000 W cm 2 [7]. Abdoli et al. [8] also performed a fully 3-D thermal-uid-stress-deformation analysis for cooling chips with 1000 W cm 2 background heat ux and up to 2000 W cm 2 heat ux at the hot spot. They reported that multi- oor microchannels are capable of cooling such chips without exceeding the maximum allowable stresses. Micro pin-ns have shown very promising results in conveying heat from multiple layers to the heat sink [9,10]. Aleri et al. [11] numerically investigated cooling of 3-D stacked chips with 50 W cm 2 background and 125 W cm 2 hot spot heat uxes. They studied the inuence and implications of the integrated water cooling, micro pin-ns distribution and sizes also inuence tem- perature of hot spots. Aleri et al. [12] in another research modelled vortex shedding in water cooling of 3-D integrated electronics. Zhang et al. [13,14] experimentally investigated effects of silicon micro pin-n heat sink with integrated TSVs in cooling high power chips. Dembla et al. [15] also studied the ne pitch TSV integration in silicon micro pin-n heat sinks for 3D ICs with 100 W cm 2 heat load. * Corresponding author. E-mail addresses: aabdo004@u.edu (A. Abdoli), gjime006@u.edu (G. Jimenez), dulikrav@u.edu (G.S. Dulikravich). Contents lists available at ScienceDirect International Journal of Thermal Sciences journal homepage: www.elsevier.com/locate/ijts http://dx.doi.org/10.1016/j.ijthermalsci.2014.12.021 1290-0729/© 2014 Elsevier Masson SAS. All rights reserved. International Journal of Thermal Sciences 90 (2015) 290e297