A Comparative Study of Modeling at Different Levels of Abstraction in System on Chip Designs: A Case Study Suryaprasad Jayadevappa, Ravi Shankar, Imad Mahgoub Department of CS&E, Florida Atlantic University, FL, USA. ({sjayadev, ravi, imad} @ cse.fau.edu) Abstract Abstraction is a powerful technique for the design and implementation of complex systems. A model developed at a higher level of abstraction allows one to tackle complexity by initially hiding the details and elaborating them later. A higher level of abstraction typically has a positive effect on the simulation speed and ease of development of the model, but could affect the accuracy of the model developed. In this paper, we study the effect of model abstraction of a peripheral device developed at a higher level of abstraction using SystemC, and at the register transfer level using Verilog. The parameters compared are accuracy, simulation speed, flexibility, time to develop, code length and ease of verification. In our study we show that by raising the level of abstraction, one not only achieves better simulation speed, flexibility, ease of verification but also reduces time to develop and shorten code length. All this is achieved while being able to maintain almost the same accuracy. 1. Introduction Present day technological advances provide us with the capability to integrate more and more functionality into a single chip. This has led to new design paradigms including, System-on-Chip (SoC), System Level Design, and Platform-based Design (PBD). In SoC designs all the functionality of a system is captured on a single chip, leading to increased performance, reduced power consumption, lower costs, and reduced size. SoC design brings with it new challenges and difficulties. The designs are large, complicated, and involve software and hardware components. These designs have to be modeled at a high level of abstraction before partitioning into hardware and software components for final implementation. From the hardware (HW) design point of view, hardware description languages (HDLs) such as Verilog and VHDL, in conjunction with hardware simulation and synthesis tools, have proven highly valuable. Efforts have been made to extend these approaches to work for multiprocessor-based SoC design, but these tend to require a significant amount of information about the partitioning of the system into coarse-grained blocks at the start. With the increased complexity new approaches seem inevitable. We are at a transition stage similar to the move from schematic-based design to hardware description language (HDL)-based design. A few years ago, just the notion of a new language (such as C) for hardware design, raised technical and suitability issues. Hardware engineers accustomed to using HDLs find it difficult to accept that a software development and modeling language such as C/C++ could be useful for hardware design. To accelerate hardware design, designers use software models of the hardware that they build. These models developed at high level of abstraction are used to validate the functionality and evaluate performance. SystemC a relatively new language, is aimed at facilitating model development above the register transfer level (RTL) [1,2]. SystemC 2.0 provides the ability to capture designs at various levels of abstraction. The single language solution to express designs at different levels of abstraction makes SystemC language a strong contender for system level design language. Built around the C++ language, SystemC inherits the reputation of C++ as a multi- paradigm language, and offers additional capabilities for HW design. SystemC is close enough to C++ to develop SW intellectual property (IP) blocks, and is well suited for developing HW soft IP’s. Earlier to SystemC, a typical design at system level was created using C/C++, Matlab, Spreadsheet or some variant. Next these designs had to be manually translated into RTL to capture the architecture. This conversion would typically lead to many design errors making previous work unfit for reuse. SystemC provides various features to perform system level modeling and simulation, which are missing in the generic HDL’s such as VHDL and Verilog. But SystemC is not intended to replace Verilog or VHDL. Supporting models at various levels of abstraction is a key feature in SystemC. Synthesizability of the SystemC models currently lacks commercial tool support. In our current work, we discuss the effect of modeling at different levels of abstractions using SystemC and Copyright © 2008 Center for Systems Integration, Florida Atlantic University.