SUPPRESSION OF HARMONIC SPIKES IN ASYNCHRONOUS SIGMA DELTA MODULATION BY RANDOMIZING HYSTERESIS WINDOW A. Aurasopon, P. Kumhom and K. Chamnongthai Department of Electronic and Telecommunication Engineering, Faculty of Engineering, King Mongkut’s University of Technology Thonburi, Bangkok 10140, Thailand E-mail: aurasopon@yahoo.com , ipinmhom@kmutt.ac.th and kosin.cha@kmutt.ac.th ABSTRACT This paper proposes to suppress the harmonic spikes in asynchronous sigma delta modulation by randomizing the hysteresis window for the distribution of the switching frequency and harmonic spectrum. The proposed scheme was examined in the dc/dc buck converter. The experimental results show that the proposed technique provides improved performance in terms of low peaks of harmonic while maintaining low output voltage ripple. 1. INTRODUCTION Pulse width modulation (PWM) has been widely used in power electronic systems. It normally operates with a fixed switching frequency, which causes power spectrum to be concentrated at multiples of the switching frequency. This gives rise to harmonic spikes that can produce unwanted effects such as acoustic noise, torque ripple and electromagnetic interference (EMI) in the power converter. Many techniques were proposed to reduce the peaks of harmonic spectrum in PWM signal, frequency modulation (FM) [1] and random pulse width modulation (RPWM) [2][3]. In FM technique, the PWM switching signal is modulated with sinusoidal signal. As a result, the power is spreaded into some side band frequencies and the level of the emission spectrum is reduced. In RPWM techniques, a random noise signal is used to control switching frequency with a constant duty ratio, pulse position in each interval of switching time or duty ratio with a fixed switching frequency. The result is the continuous distribution of spectrum output voltage and the harmonic spikes are reduced. However, these spread spectrum techniques affect the efficiency of output regulation, current and voltage ripple, which are also important to consider in applications. Sigma delta modulation (SDM) has been applied to generate PWM signal for switching power converters. The SDM has the advantage in keeping the regulation of EMI noise level with spread spectrum characteristics of second-order SDM [4]. However, the problem of noise is still exists in SDM. In the first- order SDM, there are some harmonic spikes in cases of a dc input and in cases of an ac input with a low modulation index. Therefore, the dither sigma delta modulation (DSDM) was used to avoid discrete spectrum [5][6]. In DSDM, a small dither signal is added to the input of the comparator, which produces a perturbation of the correlation between the quantization error, the input decreases, and the spectrum becomes continuous. Although the peaks of harmonic spectrum can be reduced by these techniques but it causes the distribution of noise on a pass band filter of a power converter and the duty cycle of switching period is not constant. As a result, low-frequency ripple appears in the converter output, which is not suitable for applications that require the tight output regulation, such as dc-dc converters. This paper presents the suppression of harmonic spikes in asynchronous sigma delta modulation (ASDM) by using the random noise signal added to the hysteresis window of comparator. The advantages of this technique are the constant duty ratio in every switching cycle and easy to implement on analog devices without sampling clock. The proposed method was examined in the dc/dc buck converter. The results were shown that the reduction of harmonic spikes and can be achieved with low ripple of output voltage. 2. BACKGROUNDS AND BASIC CONCEPT Fig. 1(a) shows the block diagram of ASDM, which consists of integrator and hysteresis comparator in the forward path, x(t) as input signal, y (t) as PWM signal. The ASDM is a unity feedback system. The output, and also the feedback, is a two- level digital signal v o = V . The switching points of the comparator are ho v and the integrator has time constant of . The input x (t) has been assumed a constant dc voltage illustrated in Fig1 (b) assuming that the output of hysteresis comparator starts at v o = -V. The error signal fed to the integrator is v in – (-V) and integrator output increases. The comparator output is turned “on,” v o = +V when the input reaches +v ho . The error signal applied to the integrator is v in -V. The integrator output reduced until -v ho whereupon the comparator switches “off” and the cycle repeats. Equations (1)-(5) give the on time, off time and switching frequency f s [7]. s m t v v v t l o in ho m on 1 1 2 ) ( (1)