Preventing Crosstalk Delay using Fibonacci Representation ∗ Madhu MUTYAM International Institute of Information Technology Gachibowli, Hyderabad - 500019, India madhu mutyam@iiit.net Abstract As the CMOS technology scaled down to deep sub- micron level, the crosstalk effects due to the coupling capac- itance between interconnection lines has become one of the main performance limiting factors. Several methods such as those based on routing strategies, skewing the timing of signals on adjacent wires, interleaving mutually exclusive buses, precharging the bus, and bus encoding technique, have been proposed to eliminate/reduce the crosstalk de- lay. In this work, we propose a bus encoding technique us- ing a variant of binary Fibonacci representation to prevent crosstalk delay and give a recursive procedure to generate crosstalk delay free binary Fibonacci codewords. We show that m-bit crosstalk delay free binary Fibonacci codewords are used to encode ⌊log 2 (F m+2 )⌋-bit bus, where F m+2 is the (m + 2) th Fibonacci number. So, a 32-bit bus can be encoded using 46-bit crosstalk delay free binary Fibonacci codewords. 1. Introduction The main source of crosstalk interaction between two ad- jacent wires is capacitive coupling. The increase of inter- wire coupling capacitance makes crosstalk interference a serious problem for VLSI circuits [5, 12]. The major crosstalk effects are crosstalk glitch and crosstalk delay. Crosstalk glitch occurs when there is a switch for the signal at one line and the signal at the other line is driven steady, in which case a glitch is formed at the output of the steady line. The condition for crosstalk delay is that the signal at both lines switches to the opposite direction. The result is an in- crease in transition time. Since the main focus of this work is on eliminating delay caused by crosstalk interactions, we concentrate on crosstalk delay and give an overview * This research work was supported by Science and Engineering Re- search Council, Department of Science and Technology, New Delhi, under Fast Track Proposal for Young Scientists scheme. of existing methods to eliminate/reduce it. Crosstalk de- lay is in proportion to the product of resistance and capac- itance of the interconnect wire. The capacitance of inter- connection consists of both vertical capacitance (i.e., the capacitance between the wire and the substrate) and hori- zontal capacitance (i.e., the capacitance between adjacent wires). The thickness (height) of the wires is not scaled down by as much as the width of the wires and, as the CMOS technology scaled down to deep sub-micron level, the wires are packed closed to each other, the horizontal coupling capacitances are becoming larger. Several meth- ods have been proposed to eliminate/reduce crosstalk de- lay. Some of these methods are based on routing strate- gies [6, 13, 15, 16, 17], which employ various routing tech- niques to minimize crosstalk delay within a data-path or logic block. Repeater insertion techniques are used to re- duce capacitance and resistance of long interconnections for decreasing wire delay [2, 12]. But these techniques can not solve the problem of simultaneous transitions for opposite directions. In order to overcome this problem, a bus delay reduction technique was proposed in [8]. The main idea is to prevent simultaneous opposite transitions by skewing signal transition timing of adjacent wires. A simple tech- nique to eliminate crosstalk delay is by placing a shield- ing wire between every adjacent wire. But this technique has a drawback of doubling the wiring area. Abstracted from the concept of shielding, Victor et al. have proposed a bus encoding technique [14] and gave self-shielding codes with/without memory to prevent crosstalk delay. This tech- nique was proved theoretically far better than just placing shielding wire between every adjacent wire. They showed that a 32-bit bus can be encoded with 40 wires using self- shielding codes with memory or 46 wires with memory- less self-shielding codes. Though this technique is theo- retically sound, there is no simple approach to generate the self-shielding codes. In this work, we propose a new bus encoding technique using a variant of binary Fibonacci representation and give a recursive procedure to generate crosstalk delay free binary Fibonacci codewords. The generated Fibonacci codewords Proceedings of the 17th International Conference on VLSI Design (VLSID’04) 1063-9667/04 $ 20.00 © 2004 IEEE