Selective Shielding: A Crosstalk-Free Bus Encoding Technique Madhu Mutyam International Institute of Information Technology, Hyderabad Gachibowli, Hyderabad - 500032, India mutyam@iiit.ac.in Abstract— With CMOS process technology scaling to deep submicron level, propagation delay across long on-chip buses is becoming one of the main performance limiting factors in high-performance designs. Propa- gation delay is very significant when adjacent wires are transitioning in opposite direction (i.e., crosstalk transitions) as compared to transitioning in the same direction. As crosstalk transitions have significant impact on propagation delay, several bus encoding techniques have been proposed in literature to eliminate such transitions. In this work, we propose a technique, namely, selective shielding, to eliminate crosstalk transitions. Compared to the conventional shielding technique, our technique significantly reduces the number of extra wires. We give a lower bound on the number of wires required to encode n-bit data using the selective shielding technique. We show that our technique achieves better energy savings and requires less area as compared to the other techniques. I. I NTRODUCTION As CMOS process technology advances to deep submicron region, the interconnect width and spacing reduce, which in turn increase the interconnect resistance and inter-wire capacitance. At the same time, on-chip global interconnects are increasing in length. Increase in interconnect resistance, length, and inter-wire capacitance results in large on-chip propagation delay [1], [10], [12]. Further more, propagation delay is a strong function of transitions on adjacent wires and it is very significant when adjacent wires are transitioning in opposite directions (i.e., crosstalk transitions) as compared to transitioning in the same direction. As crosstalk transitions can significantly impact the on-chip prop- agation delay, several bus encoding techniques have been proposed in literature to eliminate such transitions. A simple technique to eliminate crosstalk transitions is to insert a shield wire between every pair of adjacent data wires [3]. As there is no activity on shield wires, the shielding technique eliminates crosstalk transitions, but it requires n - 1 extra wires for a n-bit bus. Other than the shielding technique, there are many bus encoding techniques to encode data in such a way that no crosstalk transitions are present. All the existing crosstalk-free bus encoding techniques require many extra wires. In this paper, we propose a crosstalk-free bus encoding technique, namely, selective shielding, and discuss its mathematical properties and implementation issues. We show that our technique achieves better energy savings and requires less area as compared to the other techniques. The rest of the paper is organized as follows: We review analytical models for delay and energy in Section II and related work in Section III. We present the selective shielding technique in Section IV. Section V studies the properties of our coding technique and Section VI deals with the implementation issues. We discuss the delay and energy efficiency of our technique in comparison to the other existing techniques in Section VII and conclude the paper in Section VIII. II. ANALYTICAL MODELS FOR DELAY AND ENERGY We first review analytical models for delay and energy in deep submicron buses. In this paper, by assuming a n-bit parallel bus in a Transition Patterns (Δ l-1 Δ l Δ l+1 ) Relative Delay of wire l (×τ 0 ) x - x 0 ↑↑↑,↓↓↓ 1 - ↑↑,↑↑ -,- ↓↓,↓↓ - 1+ λ -↑-,-↓-,↓↓↑,↑↓↓, ↑↑↓, ↓↑↑ 1+2λ - ↑↓,- ↓↑,↓↑ -,↑↓ - 1+3λ ↓↑↓,↑↓↑ 1+4λ TABLE I CROSSTALK CLASSES ( HERE λ = C I C L AND x : {a → b | a, b ∈{0, 1}}). single metal layer, we model a deep-submicron bus as a distributed RC network with coupling capacitance between adjacent wires. A. Delay Model If d n-1···0 t is a n-bit data present on the bus, the propagation delay of the RC circuit for transmitting a n-bit data d n-1···0 t+1 is given by [5] T (dt,dt+1) = max{T l (dt ,dt+1) | 0 ≤ l ≤ n - 1}, where the delay of wire l (0 <l<n - 1) of the bus is given by T l (dt,dt+1) = τ0[(1 + 2λ)Δ 2 l - λΔ l (Δ l-1 +Δ l+1 )] where τ0 is the delay of a crosstalk-free line, λ(= C I C L ) is the ratio of the coupling capacitance to the wire-to-substrate capacitance, and Δ l is the transition occurring on line l. Δ l is equal to j - i for i-to-j transition, where i, j ∈{0, 1}. From the above equation, it is clear that data transition patterns such as 0 → 1 (or ↑), 1 → 0 (or ↓), 0 → 0 (or -), 1 → 1 (or -), dictate the propagation delay. Data transition patterns are classified into six different classes [5] based on the relative delay a wire with respect to its adjacent wires. The delay of line l of a n-bit bus, where 0 <l<n - 1, for all possible combinations of transitions is shown in Table I. From the table, it is clear that elimination of crosstalk transitions reduces the worst-case propagation delay from τ0(1+4λ) to τ0(1 + 2λ). B. Energy Model The average energy consumed per bus transfer depends on the statistical distribution of the data. The average energy consumed during a transition from a n-bit data d n-1···0 t to another n-bit data d n-1···0 t+1 is given by [4], [6] E(dt,dt+1) = CLV 2 dd [((1 + λ)Δ0 - λΔ1)d 0 t+1 +Σ n-2 l=1 ((1 + 2λ)Δ l - λ(Δ l-1 +Δ l+1 ))d l t+1 +((1 + λ)Δn-1 - λΔn-2)d n-1 t+1 ] where λ(= C I C L ) is the ratio of the coupling capacitance to the wire- to-substrate capacitance, V dd is the supply voltage, and Δ l is equal to j - i for i-to-j transition, where i, j ∈{0, 1}. 1-4244-1382-6/07/$25.00 ©2007 IEEE 618