1160 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 5, MAY 2006 A Digitally Controlled Oscillator System for SAW-Less Transmitters in Cellular Handsets Chih-Ming Hung, Member, IEEE, Robert Bogdan Staszewski, Senior Member, IEEE, Nathen Barton, Meng-Chang Lee, Member, IEEE, and Dirk Leipold Abstract—A complete digitally controlled oscillator (DCO) system for mobile phones is presented with a comprehensive study. The DCO is part of a single-chip fully compliant quad-band GSM transceiver realized in a 90-nm digital CMOS process. By operating the DCO at a 4 GSM low-band frequency followed by frequency dividers, the requirement of on-chip inductor and the amount of gate oxide stress are relaxed. It was found that a dynamic divider is needed for stringent TX output phase noise while a source-coupled-logic divider can be used for RX to save power. Both dividers are capable of producing a tight relation between four quadrature output phases at low voltage and low power. Frequency tuning is achieved through digital control of the varactors which serve as an RF DAC. Combining a MIM capacitor array and two nMOS transistor arrays of the varactors for the RF DAC, a highly linear oscillator gain which is also insensitive to process shift is achieved. The finest varactor step size is 12 kHz at the 1.6–2.0 GHz output. With a sigma-delta dithering, high frequency resolution is obtained while having negligible phase noise degradation. The measured phase noise of 167 dBc/Hz at 20 MHz offset from 915 MHz carrier and frequency tuning range of 24.5% proves that this DCO system can be used in SAW-less quad-band transmitters for mobile phones. Index Terms—Cellular phone, channel hot carrier (CHC), deep- submicron CMOS, digitally controlled oscillator (DCO), electro- migration (EM), gate-oxide reliability, GSM, mobile phone, quan- tization noise, sigma-delta modulator, varactor, voltage-controlled oscillator (VCO). I. INTRODUCTION T HE cellular phone industry recently has been growing ex- plosively. A cellular phone nowadays is not only an air modem but integrates a variety of applications such as gaming, e-mail, video streaming, and PDAs. As a result, the RF IC be- comes only a small portion of the phone and the cost of RF func- tions is driven down more than ever. In order to reduce cost, achieving a higher level integration for system-on-chip (SoC) is demanded so that power consumption, bill-of-materials such as pin count, external component count and PCB area, etc. are minimized. That is, RF functions such as RF oscillators need to be realized together with digital signal processors (DSPs), memory, digital baseband, analog baseband and power manage- ment without any additional masks for analog extensions in a CMOS process. However, what is advantageous to a DSP in a digital CMOS process, such as low voltage and thin metal in- terconnects, is disadvantageous to RF circuits due to reduced Manuscript received September 26, 2005; revised December 22, 2005. The authors are with the Digital RF Processor (DRP ™) Department, Wireless Analog Technology Center, Texas Instruments, Inc., Dallas, TX 75243 USA (e-mail: cmhung@ti.com). Digital Object Identifier 10.1109/JSSC.2006.872739 voltage headroom, low inductor , and reduced gate oxide re- liability. Furthermore, to eliminate transmitter (TX) surface- acoustic-wave (SAW) filters, the stringent requirement such as GSM TX noise emission in receiver (RX) bands is now directly applied to the TX local oscillator (LO). To alleviate these con- straints, one approach is to realize as many traditional analog functions as possible by digital logic gates. As a result, the dif- ficulties of implementing analog functions in a nanometer-scale CMOS process are greatly reduced. Instead, now, the newly im- plemented analog functions using digital logic gates can take full advantage of CMOS process scaling. In this paper, we present an RF digitally controlled oscillator (DCO) system [1], [2] which can be directly connected to an all-digital phase-locked loop (ADPLL) [3] with a straight digital interface while satisfying the stringent GSM phase noise requirements and covering all GSM quad-band frequencies be- tween 824 and 1990 MHz without any external SAW filter. The DCO system contains an oscillator core, two transmit and two receive frequency dividers as well as several clock buffers. Since at present, not every analog function in the transmit system is implemented with digital logic gates, many common questions on the analog-digital interface arise. In the rest of the paper, the analog-digital interface will be described in detail including the RF DAC characteristics, phase noise due to DAC quantization noise, spurs due to digital signal processing, and how a very fine frequency step is achieved with the DCO. In addition, reliability concerns such as gate oxide integrity (GOI), channel hot carrier (CHC) and metal electromigration (EM), as well as the output buffer serving as a pre-power-amplifier (PPA) will also be discussed. II. OVERVIEW OF THE DCO SYSTEM Shown in Fig. 1(a) is the DCO system. The DCO ASIC cell is built with only digital I/Os even for the RF outputs at PCS band (1900 MHz) since 10%–90% rise and fall time and ) of an inverter buffer in a 90-nm CMOS process is 40 ps. The DCO ASIC cell contains a DCO core oscillating at 2 GSM high-band (HB) frequencies, and frequency dividers for gener- ating TX RF outputs and LO signals for RX mixers. Since GSM is a half-duplex system, with a proper frequency planning, all GSM quad bands can be covered with one single DCO core as long as it has a 18.8% tuning range covering the frequencies between 3296 and 3980 MHz. With a reasonable margin, realis- tically, 25% of frequency tuning range is required to cover all four GSM frequency bands. Although it is typically a tradeoff between phase noise and frequency tuning range, in order to eliminate the need of an external TX SAW filter, the phase noise still needs to be 162 dBc/Hz at 20-MHz offsets from all 0018-9200/$20.00 © 2006 IEEE