A SELF-RECONFIGURING ARCHITECTURE SUPPORTING MULTIPLE OBJECTIVE FUNCTIONS IN GENETIC ALGORITHMS Charalampos Effraimidis, Kyprianos Papadimitriou, Apostolos Dollas, Ioannis Papaefstathiou Department of Electronic and Computer Engineering Technical University of Crete Chania, Greece {ceufraimidis@isc, kpapadim@mhl, dollas@mhl, ygp@mhl}.tuc.gr ABSTRACT Genetic algorithms (GA) are search algorithms based on the mechanism of natural selection and genetics. FPGAs have been widely used to implement hardware-based genetic al- gorithms (HGA) and have provided speedups of up to three orders of magnitude as compared to their software counter- parts. In this paper, we propose a parameterized partially reconfigurable HGA architecture (PPR-HGA). The novelty of this architecture is that it allows for the objective function to be updated through partial reconfiguration, and supports various genetic parameters. 1. INTRODUCTION Genetic algorithms (GA) are techniques used to find exact or approximate solutions to optimization and search prob- lems [1]. Despite the GA ability to provide good solutions to various problems, its algorithmic structure is simple. In Figure 1 each of the block modules performs a simple oper- ation: (i) the fitness module performs the evaluation of the chromosome, (ii) the sequencer module randomly selects the chromosomes, i.e. an aspect of the model under study, and passes them to the selection module, (iii) the selection module decides which of the sequenced module should ad- vance, and (iv) the mutation and crossover modules mutate and mate the selected chromosomes. The need for hardware implementation of GAs arises from the overwhelming computational complexity of prob- lems that cause delays in the optimization process of soft- ware implementations. The speed advantage of hardware and its ability to parallelize, offer great advantages to ge- netic algorithms to overcome those problems. Speedups of 1 to 3 orders of magnitude were achieved when frequently used software routines were implemented in hardware with Field Programmable Gate Arrays (FPGAs) [2]. However, those implementations were focusing on solving one spe- cific problem due to the hardware resources constraints. Over the past few years, many vendors have incorpo- rated the Partial Reconfiguration (PR) technology to certain FPGAs. This technology provides great adaptability, as part Fig. 1. Genetic algorithm flowchart of the device can be reconfigured on-the-fly without affect- ing the rest of the device. We present a parameterized par- tially reconfigurable HGA (PPR-HGA) that solves various problems by efficiently exploiting the device resources. As opposed to the prior state of the art, this architecture can load the requested objective function - also called fitness func- tion - from an external device, and thus changing the target problem while overcoming the device area constraint prob- lem. Furthermore, it has the ability to incrementally build its fitness function in order to reduce the total reconfiguration overhead. The contributions of this work are: • Optimization of an HGA and parameterization of its features for maximum problem support • Implementation of a reconfigurable mathematical unit to support multiple fitness functions • A PRM architecture that reduces bus macro usage • This work is the first to use partial reconfiguration on the GA problem