A Module Checking based Converter Synthesis Approach for SoCs Roopak Sinha, Partha S Roop and Samik Basu Abstract— Protocol conversion involves the use of a converter to control communication between two or more protocols such that desired system-level specifications can be satisfied. We investigate this problem in a formal setting and propose, for the first time, a temporal logic based automatic solution to convertibility verification and synthesis. At its core, our technique is based on local module checking and determines the existence of the converter and if a converter exists, it is automatically generated. A number of key features of our technique distinguishes it from all existing formal and/or informal approaches. Firstly, we handle both data and control mismatches using a single unifying module checking based solution. Secondly, the proposed approach uses temporal logic for the specification of correct behaviors (unlike earlier automaton based specifications) which is both elegant and natural to express event ordering and data-matching requirements. Finally, we have experimented extensively with the examples available in existing literature to evaluate the applicability of our technique in a wide range of applications. Index Terms— protocol mismatches, protocol conversion, mod- ule checking. I. I NTRODUCTION A SYSTEM-on-a-chip (SoC) contains individual processing and peripheral components (called intellectual property or IP blocks) connected together using a common bus [8]. Components in a SoC are usually developed in isolation and may follow independent communication protocols. Therefore, when several components are interconnected, it is possible that their may suffer from protocol mismatches [11]. Mismatches occur when the exchange of control signals and/or data between components is not consistent with the intended behaviour of their interaction [8], [15], [18] (leading to control and/or data mismatches). In order to resolve mismatches, it is required that mismatched components be redesigned to achieve desired system-level be- haviour. This is usually a very expensive process. Due to this overhead, protocol conversion, a term broadly used to refer to techniques that resolve mismatches without requiring manual modification of components, has been studied extensively for over two decades [3], [8], [15], [16], [19]. Protocol conversion typi- cally involves the automatic generation of extra glue-logic, called a converter, to control the communication between components in order to satisfy system-level behaviour. Consider the example of a SoC that uses the AMBA high-performance bus (AHB) [8] to connect two masters - a producer processor and a consumer processor. These two processors in the SoC [20] communicate using the slave RAM block to read/write shared data, as shown in Roopak Sinha is a PhD student at the Department of Electrical and Computer Engineering, University of Auckland, rsin077@ec.auckland.ac.nz Partha S Roop is a Senior Lecturer at the Department of Electri- cal and Computer Engineering, University of Auckland, New Zealand. p.roop@auckland.ac.nz Samik Basu is an Assistant Professor at Department of Computer Science, the Iowa State University. sbasu@cs.iastate.edu Fig. 1. However, the masters and slave have inherent control and data mismatches (explained in later sections), which prevent their integration into the AHB system system. Protocol conversion, in this case, will look at creating a converter for each master (shown in Fig. 1), such that mismatches can be eliminated. Master 1 Master 2 Slave B U S Arbiter Converter 1 Converter 2 Producer Consumer Memory AMBA AHB Fig. 1. Protocol conversion overview A formal protocol conversion technique concerns itself with a range of issues. Firstly, participating protocols and their interac- tion, and specifications must be formally described. A protocol conversion technique must also be able to detect mismatches (mis- match detection) and have an algorithm to automatically generate converters if mismatches exist (converter generation). Additional issues include determining scope–the range of mismatches that can be handled, converter existence–which checks whether a converter to resolve mismatches exists, and converter correct- ness–which checks whether a given converter indeed bridges mismatches. The answers to the above questions differ between individual protocol conversion techniques. Related Work. Existing protocol conversion techniques can be broadly categorized as informal or formal. Informal approaches like [2]–[4] and [17] lack mathematical rigor, have very restricted scope and focus mainly on converter generation without address- ing the questions of converter correctness and existence. Formal approaches, like [8], [10] and [19], on the other hand are based on mathematical techniques and proofs and solve protocol conversion within well-defined but restricted scopes, that differ for each technique. [19] present a game-theoretic formulation to resolve control mismatches between protocols with only unidirectional communication and do not address data mismatches. [8]- [9] provide synchronous protocol automata to precisely model pro- tocols, and their solution, based on checking for a compatibility relation between protocols, can only handle a restricted set of data mismatches along with control mismatches. Additionally, model- checking based verification for proving the correctness of the synthesized converter is performed as an additional step. In [10], a hybrid simulation/verification approach to protocol conversion in SoC designs is proposed, where both simulation and formal 21st International Conference on VLSI Design 1063-9667/08 $25.00 © 2008 IEEE DOI 10.1109/VLSI.2008.109 497 21st International Conference on VLSI Design 1063-9667/08 $25.00 © 2008 IEEE DOI 10.1109/VLSI.2008.109 492 21st International Conference on VLSI Design 1063-9667/08 $25.00 © 2008 IEEE DOI 10.1109/VLSI.2008.109 492 21st International Conference on VLSI Design 1063-9667/08 $25.00 © 2008 IEEE DOI 10.1109/VLSI.2008.109 492 21st International Conference on VLSI Design 1063-9667/08 $25.00 © 2008 IEEE DOI 10.1109/VLSI.2008.109 492 21st International Conference on VLSI Design 1063-9667/08 $25.00 © 2008 IEEE DOI 10.1109/VLSI.2008.109 492 21st International Conference on VLSI Design 1063-9667/08 $25.00 © 2008 IEEE DOI 10.1109/VLSI.2008.109 492