Distribution and generation of traps in SiO 2 /Al 2 O 3 gate stacks Isodiana Crupi a, * ,1 , Robin Degraeve b , Bogdan Govoreanu b , David P. Brunco c , Philippe Roussel b , Jan Van Houdt b a MATIS CNR-INFM, Catania, Italy b IMEC, B-3001 Leuven, Belgium c Intel Assignee at IMEC, B-3001 Leuven, Belgium Available online 16 February 2007 Abstract In this work we combine charge-pumping measurements with positive constant voltage stress to investigate trap generation in SiO 2 / Al 2 O 3 n-MOSFET. Trap density has been scanned either in energy or in position based on charge-pumping (CP) measurements per- formed under different operating conditions in terms of amplitude and frequency of the gate pulse. Our results have revealed that the traps are meanly localized shallow in energy level, deeper in spatial position and they are mostly generated near the Si/SiO 2 interface. Ó 2007 Elsevier Ltd. All rights reserved. 1. Introduction A lot of interest has been devoted over the past few years to high-k materials as a replacement for conventional SiO 2 [1]. Among these dielectrics, alumina is very attractive for flash memory applications [2]. In this paper we present our study, based on charge pumping (CP) measurements, to investigate the distribution and generation of traps within SiO 2 /Al 2 O 3 dielectric stack. Since CP technique has been extensively used in the past to characterize the Si/SiO 2 interface [3] and only recently proposed for thin stacked dielectrics [4–6], as a first step of our work we compare SiO 2 /Al 2 O 3 with a reference SiO 2 layer. By increasing the amplitude, as well as lowering the frequency of the gate pulse, we measure an increase of the charge recombined per cycle (Q CP ) in SiO 2 /Al 2 O 3 devices not observed in the SiO 2 case. Finally, we combine CP with constant voltage stress (CVS) measurements to investigate the trap generation rate. 2. Devices and experiments Dual stacks MOS transistors were fabricated using a conventional CMOS process flow with a poly-Si gate. The dielectrics were prepared by atomic layer chemical vapor deposition (ALCVD) of 8 nm Al 2 O 3 on top of 1 nm chem- ically grown SiO 2 . All the devices were subjected to post deposition annealing (PDA) at 900 °C in N 2 . For compari- son, devices with 8.5 nm thermally grown SiO 2 as the gate dielectric were also made. On these devices we performed CP and CVS measure- ments under different operating conditions at room tem- perature. 3. Results and discussions Figs. 1 and 2 show the different behaviors of SiO 2 /Al 2 O 3 and SiO 2 stacks when pulse trains of various amplitudes but also at different frequencies are applied to the gate electrode. In particular, we have performed base level CP measure- ments by applying pulses with frequency of 1 MHz and amplitude going from 2 to 3 V and from 2 to 2.5 V on Si/SiO 2 /Al 2 O 3 and on Si/SiO 2 stacks, respectively. In Fig. 1 we report the difference between the Q CP acquired 0026-2714/$ - see front matter Ó 2007 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2007.01.013 * Corresponding author. Tel.: +39 095 3785289; fax: +39 095 3785231. E-mail address: Isodiana.Crupi@ct.infn.it (I. Crupi). 1 Dipartimento di Fisica e Astronomia, Universita ` di Catania, via S. Sofia 64, 95123 Catania, Italy. www.elsevier.com/locate/microrel Microelectronics Reliability 47 (2007) 525–527