On the Selection of Efficient Arithmetic Additive Test Pattern Generators S. Manich, L. Garcia, L. Balado, E. Lupon, J. Rius, R. Rodriguez, J. Figueras Universitat Politècnica de Catalunya Diagonal, 647, P9, 08028 Barcelona, SPAIN manich@eel.upc.es Abstract Built-in self-test (BIST) strategies require the implementation of efficient test pattern generators (TPG) which allow the excitation and observation of potential faults in the circuit. Arithmetic additive TPGs (AdTPG) allow existing internal datapaths to be reused to perform this operation without a penalty in the circuit area. AdTPGs are configured by means of triplets: a combination of seed, increment and number of times the increment is added to the seed. Since the selection of triplets is crucial to the quality of the test vectors obtained and the test resources used, an emerging research interested in the topic is observed. In this paper, a method for generating efficient triplets which enable a reduction of memory requirements and test application time for a given fault coverage (FC) level is presented. 1. Introduction Testing large, multimillion transistor chips are one of the key issues in current integration levels. Embedded test solutions changing the classical distribution of Automatic Test Equipment (ATE) and Circuit Under Test (CUT) functions [1] [2] [3] are growing at a rapid rate. At System on Chip (SoC) level, the integration of different BIST techniques is a challenge for designers, who are proposing access mechanism solutions and device level scheduling to simplify the coordination of all these test resources [4]. Moreover, to reduce BIST area overhead and perform at-speed tests, researchers are studying the possibility of re-using functional cells in testing approaches [5] [6] [7] [9]. New BIST schemes using internal cells, as processor cores are receiving growing attention. Microprocessor based BIST consists in the execution of different algorithms by the processor, with the objective of testing subsystems of the circuit [8]. The embedded processor can operate in multifunction mode, i.e. as a pattern generator and sequencer, as a comparator or signature generator, among others [5]-[9]. The use of arithmetic generators like TPGs instead of LFSR was first proposed by Gupta, Rajski and Tyszer [10] [11]. Stroele [12], working with adders as generators, proposed a procedure for obtaining seed and increment values to reduce test length for a given set of hard-to-detect faults. The idea of functional pattern generation based on arithmetic generation with different arithmetic modules has recently been proposed in [13], [14] and [15]. Tools based on genetic algorithms and set covering problems are proposed to compute multiple seeds with different modules, coverage and test length targets. Furthermore, in [16] a similar reseeding strategy is used to generate patterns suitable for random-pattern resistant faults: on-the-fly generation of seeds is proposed by means of a special circuitry that complements a certain number of bits at a given time point. In this paper, a new approach for test pattern arithmetic additive generation (AdTPG) is proposed. This method, named LUCSAM, is based on a greedy algorithm that selects the best triplets, a combination of (seed, increment and length), of the datapath that allows a specified fault coverage (FC) level to be reached. The advantage of this method lies in the use of a special type of triplets where the increment is derived from the seed using a simple transformation. Since less information is required, memory size can be reduced. Thanks to the reduction of the search space of triplets, the possibilities of obtaining good results for the greedy algorithm increase. However, no negative impact (loss of detection capability of test vectors) is observed in large runs (i.e. more than 50 vectors) as a result of using this special type of triplets. The rest of the document is organized as follows. Section 2 is devoted to the arithmetic generator structure and the re- seeding action. In section 3 the problem is stated and the metrics for evaluating the impact of the method are proposed. Section 4 discusses two basic properties of the additive generation employed in the method proposed. Section 5 describes the LUCSAM method and section 6 presents results. Finally, in section 7 the conclusions of the paper are summarized. 2. Arithmetic Additive TPG The arithmetic additive TPG (AdTPG) principle of operation has been widely used [10]-[16]. It is based on the iterative addition of a constant increment to a seed. AdTPGs are conceived to be executed in reused datapaths existing in ICs, like the one illustrated in Figure 1, in order to minimize