Data memory management in partial dynamically reconﬁgurable systems A. Montone, Vincenzo Rana and M.D. Santambrogio DEI - Politecnico di Milano e-mail: alessio.montone@dresd.org e-mail: {rana, santambr}@elet.polimi.it ABSTRACT This paper aims at introducing a novel approach for the management of processor data memory in reconﬁgurable systems. The proposed approach allows the individual man- agement of separated data and the dynamic update of the memory with a partial bitstream. By following this way it is possible to create a system in which several master components (e.g., soft-processors or hard-processors) can be dynamically conﬁgured and in which their memory can be dynamically changed. In the ﬁrst section the reconﬁgurable scenario and its problems concerning to memory manage- ment will be introduced. The following sections will describe the state of the art and the development details of the tool that implements the proposed approach. Finally, a set of ex- perimental results will be presented and conclusive remarks will be drawn. 1. INTRODUCTION In recent years, the evolution of reconﬁgurable devices has brought to signiﬁcantly increase their size, capacity and performance [1, 2]. The most commonly used reconﬁgurable devices are Field Programmable Gate Arrays, FPGAs, em- ployed both as a component of a more complex system (play- ing the role of a co-processor), and as main architecture itself integrating most of the components of the system. In addi- tion to permitting an unlimited number of reconﬁgurations, FPGAs can also be partially and dynamically reconﬁgured: this means that single portions of the architecture can be modiﬁed without blocking the entire system execution. In a such MPREs architectures, partial dynamic reconﬁgura- bility can be exploited in order to create a more ﬂexible system, examples can be found in diﬀerent works i.e., [3–5]. Partial dynamic reconﬁgurability allows to change part of a systems without preventing the rest of the system from continuing the execution of its tasks. In a Multi Process- ing Reconﬁgurable Elements (MPRE) architecture the most obvious reconﬁguration is the replacement of a PE with an- other one. Hence according to the system requirements one (or more) processing element can be replaced by another in order to optimize an objective function (e.g. through- put, response time and so on). The reconﬁguration driver can take several inputs from the environment and from the system’s runtime conditions and, using diﬀerent policies, it can decide which Processing Elements (PEs) will be changed and when. In such a scenario, a larger number of complex components can be mapped at the same time into the same device. One of the main drawback of this context can arise when several master components have to work at the same time on the same device, since it is necessary to individu- ally manage their memory data. In order to take advan- tages from the high ﬂexibility of a reconﬁgurable system each component has to be individually conﬁgured with its memory (data and/or instruction), but this is not possible with standard tools for the design of reconﬁgurable systems, since they are able to create a conﬁguration bitstream for the data conﬁguration just in complete bitstreams, and not in partial ones. For this reason it is impossible to adopt these tools for the design of partially dynamically reconﬁg- urable systems in which memory data has to be partially and dynamically changed. Previous works in this area mainly focused their atten- tion on the manipulation of bitstreams content on Xilinx FPGAs devices. Inside Virtex family documentation [6] there are equations for single BRAM-Block content mem- ory manipulation. These equations allow to ﬁnd, to insert or to modify memory information inside a conﬁguration bit- stream, but they are not valid for Virtex II FPGAs families and more recent ones (e.g., Virtex-4 [1] and Virtex-5 [2]). Furthermore these documents do not explain how several BRAM Block create a contiguous addressable memory ad- dress space. A more recent work about bitstreams manip- ulation can be found in [7]. Equations for Virtex II (Pro) are presented here, but they allow only to address frames (also according with [8]) and provide no information about single bit position and contiguous memory space of BRAM- Blocks set. No other studies have been performed on bit- stream analysis tailored for BRAM content manipulation on more recent Xilinx FPGAs families. This paper proposes a novel approach for BRAM-Block content manipulation for Xilinx Virtex II and Virtex II Pro FPGAs families, [8]. It consists in a mapping procedure that allows the creation of a bitstream able to conﬁgure only BRAM Blocks, leaving other logic unaltered. This procedure takes in input the data needed to ﬁll the memory and the list of BRAM-Block that have to be used. Therefore, the proposed approach al- lows to decouple logic conﬁguration from BRAM memory content conﬁguration (e.g. one can change code executed by a processor without having to conﬁgure the processor logic again). Such a feature may result in the partitioning of conﬁguration bitstream in two parts: a bitstream able to conﬁgure just the logic [9] and a second bitstream able to conﬁgure just the BRAM content. Due to this approach the logic can be changed in order to perform diﬀerent com- putation on the data stored in BRAMs, or it can remain unchanged while the memory content can be updated in or- der to perform the same computation on diﬀerent input data