IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 1, JANUARY 2010 201 Noise-Margin Analysis for Organic Thin-Film Complementary Technology Dieter Bode, Cédric Rolin, Sarah Schols, Maarten Debucquoy, Soeren Steudel, Member, IEEE, Gerwin H. Gelinck, Jan Genoe, and Paul Heremans Abstract—Parameter variation in organic thin-film transistor (OTFT) technology is known to limit the yield of digital circuits. It is expected that complementary OTFT technology (C-TFT) will reduce the sensitivity to parameter variations. In this paper, we quantify the dependence of yield on transistor parameter varia- tions for C-TFT and compare it to unipolar logic. First, a basic inverter model is developed and fitted to measured transfer char- acteristics of organic complementary inverters. Next, the inverter model is used in numerical simulations to determine how the noise margin of the inverter, a measure for its reliable operation, changes as a function of transistor parameter variations. The noise margin is significantly improved with respect to p-type-only in- verters with similar parameters. Finally, we perform circuit-level yield predictions as a function of parameter spread using the noise-margin simulations performed earlier. Index Terms—Complementary circuits, n-type organic thin-film transistor (n-type OTFT), yield estimation. I. I NTRODUCTION O VER THE last few years, the demonstration of circuits based on organic thin-film transistors (OTFTs) has shown the potential of this technology [1]–[3]. Considerable parameter variation is however observed [4]. This variation can cause a loss of yield [5], generally referred to as soft yield loss. Therefore, in view of today’s research interest in organic com- plementary logic [complementary OTFT technology (C-TFT)] [6]–[13], we quantify in this paper the reduced sensitivity of C-TFT (soft) yield to transistor parameter variation. Further- more, we compare it to the case of unipolar p-type-only TFT technology (p-TFT). In the approach taken, a model is first derived for C-TFT inverter stages on the basis of a compact transistor model [14]– [17]. Subsequently, the model is used to determine the noise Manuscript received April 17, 2009; revised September 25, 2009. First pub- lished November 24, 2009; current version published December 23, 2009. This work was supported in part by the European-funded Integrated Project FLAME under Grant FP7-ICT 216546. The work of D. Bode and M. Debucquoy was supported by the Institute for the Promotion of Innovation through Science and Technology in Flanders (IWT-Vlaanderen). The work of S. Schols was supported by FWO Vlaanderen. The review of this paper was arranged by Editor J. Kanicki. D. Bode, S. Schols, M. Debucquoy, and P. Heremans are with the Interuniver- sity Microelectronics Center (IMEC), 3001 Leuven, Belgium, and also with the Department of Electrical Engineering, Katholieke Universiteit Leuven, 3001 Leuven, Belgium (e-mail: dieter.bode@imec.be). C. Rolin is with IMEC, 3001 Leuven, Belgium, and also with PCPM, Université Catholique de Louvain, 1348 Louvain-La-Neuve, Belgium. S. Steudel and J. Genoe are with IMEC, 3001 Leuven, Belgium. G. H. Gelinck is with TNO-Holst Center, 5605 Eindhoven, The Netherlands. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2009.2035546 margin [18]–[21] of those inverters for different values of the transistor parameters. This noise margin is generally used as a measure for the sensitivity of the inverter operation to external noise. In this paper, however, we study the reduction of the noise margin as transistor parameters deviate from the expected values, and we deduce from this analysis the probability of successful operation of an inverter in the presence of a large parameter spread. This probability of successful operation is finally used to study circuit-level soft yield and to predict yield as a function of circuit complexity. II. I NVERTER MODEL A. Equations of the Inverter Model The static inverter model, used for the noise-margin analysis, is derived by equating the current through the p-type transistor to the current through the n-type transistor [15], [16] I DS n = −I DS p . (1) In Appendix, this equation is solved for the different regimes of operation of the transistors, using the SPICE2 level-1 model, including the parameter λ n,p that describes the finite output resistance, as described in [17]. The different regimes of opera- tion for both transistors—subthreshold, saturation, and linear regimes—result in five regimes for the inverter (see Fig. 1). Note that V DD is assumed to be positive and larger than V T n − V T p . If the latter condition is not met, over the entire input voltage range, at least one of both transistors will be in the subthreshold regime, and this regime is not accurately described by the transistor model used. B. Validation of the Inverter Model To verify the relevance of our inverter model, comple- mentary organic inverters have been fabricated. The inset of Fig. 3 shows the structure of these inverters. A highly n-type doped silicon wafer is used for the gate contact of the in- verter. A 120-nm-thick thermally grown SiO 2 layer forms the gate dielectric. Prior to organic semiconductor deposition, the SiO 2 is treated with a thin polymer layer of Zeonex 480R [22], [23] spin coated from a 0.1-wt% solution in toluene. Next, pentacene is evaporated on half of the substrate for the p-type transistors, and subsequently, N,N ′ -ditridecyl-3,4,9,10- perylenetetracarboxylic diimide (PTCDI-C 13 H 27 ) [24], [25] is deposited on the other half of the sample. To finish the p-type transistors, Au contacts are evaporated on the pen- tacene through a shadow mask. Finally, the n-type transistors 0018-9383/$26.00 © 2009 IEEE Authorized licensed use limited to: IMEC. Downloaded on December 23, 2009 at 08:59 from IEEE Xplore. Restrictions apply.