Impact of Gate Oxide Complex Band Structure on n-Channel III-V FinFETs Dax M. Crum*, Amithraj Valsaraj, Leonard F. Register, Sanjay K. Banerjee The University of Texas at Austin, USA *E-mail: dcrum@utexas.edu Bhagawan Sahu, Zoran Krivakopic, Srinivasa Banna, Deepak Nayak GlobalFoundries USA Inc., USA Abstract—FinFET geometries have been developed for the sub-22 nm regime to extend Si-CMOS scaling via improved electrostatics compared to planar technology. Moreover, engineers have incorporated high-k oxide gate stacks. Beyond leakage current, less discussed is the impact of the gate oxide’s com- plex band structure on the device performance. However, it defines the boundary condition for the channel wavefunction at the interface, which, in turn, affects the quantum confinement energy for channel electrons. Here we show that the ON-state performance of n-channel FinFETs may be sensitive to the oxide’s complex band structure, especially with light-mass III-V channel materials, such as In 0.53 Ga 0.47 As. We study this effect using an ensemble semi-classical Monte Carlo device simulator with advanced quantum corrections for degeneracy and confinement effects. Our simulations suggest that using a surface oxide with a heavy effective mass may lower the channel carrier confinement energies, mitigating unwanted quantum side-effects that hinder device performance. Ultimately, future high-k stacks may benefit from oxide gate stack heterostructures balancing effective mass and dielectric permittivity considerations. I. I NTRODUCTION Physical limits [1] have become the pressing chal- lenge for Si planar metal-oxide-semiconductor-field-effect- transistors (MOSFETs) when considering future device nodes. Simply reducing device dimensions is no longer sufficient, as nano-scale planar CMOS devices suffer from debilitating short-channel effects (SCE) [2]. Poor electrostatic control can lead to substantial drain-induced barrier lowering (DIBL) and degraded device subthreshold swing (S), as well as limiting transconductance (g m ), contributing to poor ON/OFF ratios. Incorporation of new three-dimensional (3D) geometries, especially that of the 3D fin-shaped MOSFET (FinFET) [3], has extended the scaling life of MOSFETs via improved gate control, as well as reduced on-chip surface area. FinFETs are likely to drive scaling in future device nodes [4]. Moreover, high dielectric constant (high-k) oxide stacks have improved gate-to-channel capacitive coupling, allowing for reduced ef- fective electrostatic oxide thicknesses (EOT), despite increased physical thicknesses to prevent tunneling. Alternate channel materials also are being considered widely for future device nodes, such as III-Vs for n-channel devices in particular [5]. III-Vs may provide a performance boost versus Si in the ON-state via higher bulk mobilities and higher thermal injection velocities associated with lighter masses, the latter being more important approaching the ballis- tic limit. In particular, In 0.53 Ga 0.47 As, which is lattice-matched to fabrication-friendly InP [6], provides Γ-valley electrons with an effective mass of m * Γ =0.047 m e . However, for deeply- scaled devices a host of quantum mechanical effects may diminish the otherwise expected advantages. Considerations of the Pauli Exclusion Principle lead to reduced quantum/density- of-states (DOS) capacitance (C q ), while quantum confinement reduces intervalley separations, increases phonon scattering rates, and decreases electrostatic capacitance as the carriers are shifted further from the interface. In this paper, we show that the choice of gate oxide may affect device performance not just through the electrostatics but also through these quantum confinement effects, as it es- tablishes the boundary conditions on the channel wavefunction. To this end, we use the ensemble semi-classical Monte Carlo (EMC) simulation tool with advanced quantum corrections that was described in [7] to model nano-scale In 0.53 Ga 0.47 As FinFETs. We find that use of lighter gate oxide effective masses (m * ox ) actually leads to increased quantum confinement effects, including increased scattering and intervalley transfer, and, thus, reduced ON-state performance. In this way, we find that the otherwise expected advantage of higher-k materials may be minimized by often-associated lighter masses, and that oxide stacks combining higher-mass surface dielectrics with higher-k dielectric over-layers could prove optimal. II. MODEL AND DEVICE- LEVEL QUANTUM CORRECTIONS To efficiently and accurately model 3D FinFETs, with In 0.53 Ga 0.47 As channels including non-parabolic band struc- tures, an appropriate simulation methodology is EMC [8], [9]. EMC seamlessly handles regimes of transport from diffusive through ballistic, while including all relevant scattering pro- cesses, including long-range polar optical phonon scattering that can dominate electron scattering in III-Vs. Our software generates complex 3D geometries, such as the model FinFET considered in this study (Fig. 1), with material- specific band structures—valley edge separations, masses, and non-parabolicity constants—and other parameters borrowed from other studies [10]–[13]. Our EMC calculations pro- vide quantum corrections to capture the essential physics of important quantum confinement effects, in addition to Pauli Exclusion considerations in degenerate systems. A. Quantum corrections for degeneracy Scaling principles demand degenerate dopant densities approaching solid-solubility limits. For In 0.53 Ga 0.47 As chan- nels, we choose an activated source/drain dopant density of