Application-Specific Topology Design Customization for STNoC Gianluca Palermo †‡ Cristina Silvano † Giovanni Mariani ‡ Riccardo Locatelli ♯ Marcello Coppola ♯ † Politecnico di Milano - Dipartimento di Elettronica e Informazione ‡ ALaRI - Faculty of informatics - University of Lugano ♯ STMicroelectronics - Advanced System Technology Abstract Customized network-oriented communication architec- tures have recently become a must to support high band- width SoCs. To this end, a corresponding communication design flow is necessary to support the design space ex- ploration of complex SoCs with tight design constraints. In order to exploit the benefits introduced by the NoC ap- proach for the on-chip communication, the paper presents a Pareto Simulated Annealing (PSA) approach for the cus- tomization of the network topology. The proposed PSA ap- proach has been applied to STNoC, the Network on-Chip developed by STMicroelectronics. Starting from the ring topology, the proposed application-specific design flow tries to find a set of customized topologies (optimized in terms of performance and area/energy overhead) by adding custom links up to the spidergon topology. 1 Introduction Design-time specialization is an important factor for the Network-on-Chip (NoC) [1, 4] paradigm. In fact, most NoC architectures have been specifically developed either for one embedded application or as a platform for a small class of applications and consequently, the traffic charac- teristics cover an important role for the network customiza- tion [5–8]. Designing a NoC architecture, one of the first steps to be done is the topology selection. Due to the regularity characteristics and the success in macro-networks, standard topologies (such as 2D mesh and torus) are selected as basis for the on-chip network infrastructure. However, in the on- chip domain, the connectivity theoretically offered by stan- dard topologies cannot be fully exploited due to the nature of communication traffic in real embedded applications. In other word, we can pay in area and power overhead more than the performance benefits that the topology can offer. In some application-specific scenarios, an approach based on the customization of simple standard topologies can be more effective in terms area/energy/performance trade-off with respect to more complex standard topologies. In this direction, the proposed approach starts from a simple topology (such as ring) for the following application-specific topology customization process to boost the network performance without requiring the area and energy overhead of more complex networks. In par- ticular, this paper presents an application-specific approach for the topology customization of STNoC [2, 10], the Net- work on-Chip developed by STMicroelectronics. Starting from the ring topology, the proposed technique tries to find the optimal topology in the STNoC family of topologies (ranging from ring to spidergon) by adding a set of cus- tom links to optimize the network performance on the tar- get application. The main purpose of the paper is not to propose the STNoC architecture, that has already been pre- sented in [2, 10], but to proposed a design methodology to customize STNoC for application-specific designs. The paper is organized as follows. In Section 2 and 3, the problem description and the proposed approach are de- scribed respectively. The experimental results and conclu- sions are shown in Section 4 and 5. 2 Problem Definition Before starting the description of the design flow used for the STNoC topology customization, let us introduce some theoretical concepts. First of all, we define two main graphs that are the object of our discussions: the core graph, used to describe the target application, and the topology graph, used to describe the network topology. The core graph (also called application graph or commu- nication graph) is a directed graph, G(V,E) where each ver- tex v i ∈ V represents a core and each direct edge (v i ,v j ), denoted as e i,j ∈ E, represents the communication between the cores v i and v j . The weight of the edge e i,j represents the bandwidth of the communication from v i and v j . The NoC topology graph is a directed graph P (U, F ) where each vertex u i ∈ U represents a node in the topology and each direct edge (u i ,u j ), denoted as f i,j ∈ F , repre- 1