3D Design For Test Architectures Based on IEEE P1687 Yassine Fkih (1,2) , Pascal Vivet (1) , Bruno Rouzeyre (2) , Marie-Lise Flottes (2) , Giorgio Di Natale (2) , Juergen Schloeffel (3) (1) CEA-Leti, MINATEC Campus, F38054, Grenoble France (2) LIRMM, Univ Montpellier II/CNRS, Montpellier France (3) Mentor Graphics, Hamburg, Germany Abstract—3D stacked integrated circuits based on Through Silicon Vias (TSV) are promising with their high performances and small form factor. However, these circuits present many test issues. In this paper we propose a novel 3D Design for Test (DFT) architecture based on IEEE P1687. The proposed test architecture enables test at all 3D fabrication levels: pre, mid, and post-bond levels. We discuss 3 DFT architecture proposals and we show one practical implementation using a commercial EDA tool. Key words: 3D IC, DFT, pre-bond test, post-bond test, JTAG, IEEE 1149.1, IJTAG, IEEE P1687 I. INTRODUCTION The stacking process of integrated circuits using TSVs (Through Silicon Via) is a promising technology that keeps the development of the integration more than Moore’s law, where TSVs enable to tightly integrate various dies in a 3D fashion. Regarding applications, 3D stacking allows a wide range of new SoC applications, such as heterogeneous stacking (Digital, Memory, RF, Mems); Interposers for multi- chip connection are becoming similar to a silicon board. The first upcoming 3D applications are mainly the WideIO DRAM 3D memory interface for high throughput and low power memory-on-logic stacking [1]. Nevertheless, 3D integrated circuits present many test challenges including the test at different levels of the 3D fabrication process: pre-, mid-, and post- bond tests. Pre-bond test targets the individual dies at wafer level, by testing not only classical logic (digital logic, IOs, RAM, etc) but also unbounded TSVs. Mid-bond test targets the test of partially assembled 3D stacks, whereas finally post-bond test targets the final circuit. It is generally admitted that a 3D test flow [2] should involve test procedures at all stacking levels of the 3D components. In this paper we present a 3D DFT architecture based on IEEE P1687 and auto die-detection mechanism. The paper is organized as follows. In section II we introduce the state of the art of Design For Test of 3D integrated circuits, in section III we give an overview of the IEEE P1687 standard, in section IV we show three DFT proposals based on IEEE P1687, in section V we show practical implementation of a 3D circuit on a passive interposer, and in section VI we give conclusions and future work. II. STATE OF THE ART Many DFT architectures were proposed for testing 3D integrated circuits. The first papers treated: pre-bond test of 3D processors using scan islands and so called layer test controller (LTC) [3], scan chain optimization approaches [4], and other test issues like test cost optimization [5]. More recent works propose die level wrappers based either on IEEE 1500 [6] or IEEE 1149.1 [7] test standards that allow 3D test at all levels: pre-, mid-, and post-bond. The test architecture has mainly three features: use of dedicated probe pads for non- bottom dies to perform pre-bond die testing, use of “TestElevators” to drive test signals up and down during post- bond test, and use of a hierarchical WIR (Wrapper Instruction Register) chain to configure test interconnects. These features satisfy 3D circuits testing requirements but can be improved to avoid the configuration time of the hierarchical WIR especially for mid-bond and post-bond tests. On the remainder of this paper, we will propose 3D test architecture proposals based on IEEE P1687 (IJTAG) standard using automatic die-detection mechanism. III. OVERVIEW OF THE IEEE P1687 STANDARD The main purpose of the IEEE P1687 standard, also called IJTAG, is to develop a methodology for access to embedded test and debug features, via the IEEE 1149.1 Test Access Port (TAP) [8]. This means that in IEEE P1687 JTAG signals (TRST*, TCK, TMS, TDI, and TDO), and JTAG logic including: IR (Instruction Register) and associated decoder, TAP Controller, and DR (Data Registers) are used. Additional logic is added to the JTAG circuitry, in order to enable the access to embedded DFT instruments [9]. In IEEE P1687 it is essentially a Test Data Register (TDR) called Gateway which is added to control embedded instruments dynamically. The configuration is done on 2 steps: the first step is to select the Gateway instruction by shifting its corresponding op-code in the shift-IR state on the JTAG finite state machine [10]. The second step is to configure SIBs (Segment Insertion Bits) by shifting the configuration sequence in the shift-DR state [8,10]. This work was funded thanks to the French national program 'programme d’Investissements d’Avenir, IRT Nanoelec' ANR-10-AIRT-05