Calibrating Bulk Built-in Current Sensors for Detecting Transient Faults R. Possamai Bastos, G. Di Natale, M. L. Flottes, B. Rouzeyre LIRMM (Université Montpellier II / CNRS UMR 5506) Montpellier, France {bastos, dinatale, flottes, rouzeyre}@lirmm.fr Abstract – This work presents a novel circuit for detecting transient faults in combinational and sequential logic. The detection mechanism features a built-in current sensor connected to the bulks of the monitored logic. The proposed circuit was optimized in terms of power consumption and enhanced with low-power sleep-mode. In addition, a calibration method for bulk built-in current sensors is presented. Overhead results indicate an increase of only 15% in power consumption which represents an improvement of almost factor 6 compared to similar existing sensor. Keywords – built-in current sensors; transient faults; soft errors; fault attacks; concurrent error dectection schemes I. INTRODUCTION Higher error resilience is expected from an increasing number of integrated systems while, at the same time, ultra- deep submicron technologies make these systems more and more sensitive to natural aging processes or environment sources like radiations from cosmic origin or every day material [1]. In addition to these natural phenomena, malicious fault-based attacks can be used to bypass security mechanisms of secure systems and extracting information on confidential data [2]. Both these natural or malicious phenomena on integrated circuits can induce transient effects that provoke bit- flips of stored results during the system lifetime. Until the early 2000’s, researches on transient faults focused essentially on memory elements, which were considered the system’s most vulnerable circuits. Many concurrent error detection and/or correction mechanisms were proposed to mitigate soft errors induced by transient faults in memory cells. In the last decade, however, more sensitive deep-submicron technologies as well as the increasing demand in terms of digital security have also pushed for the development of countermeasures against transient faults in combinational parts of the circuits. These faults indeed can propagate up to storage elements and thus cause soft errors as well. On the other hand, if the transient fault does not induce any error due to an electrical, logical or latching-window masking effect, its detection is crucial all the same in secure applications since the fault itself reveals an attempt of attack. Coping with transient faults by using mitigation techniques at different abstraction levels of the design is today the trend in order to efficiently protect integrated systems [3][4]. The idea behind is the avoidance of costly fault-tolerance mechanisms like tripe modular redundancy, taking advantage of cheaper mitigation techniques that ensure satisfactory soft-error coverage for the system’s most recurrent operations. This modern strategy is exemplified through system’s recovery schemes fired in function of the indication of concurrent error detection (CED) circuitries. CED mechanisms designed at transistor or gate level guarantee an early detection, as soon as the faults happens, preventing more critical failure scenarios such as the induction and propagation of multiple errors to other clock cycles, stages, or parts of the system. In case of misbehavior, the generated error flag is able to activate, for instance, recovery machines already implemented in modern systems for dealing with branch misprediction [3][4]. Thereby, faulty operation can be repeated in fault-free conditions, adapting the system to perform again its normal computational sequence. This paper proposes a new low-cost CED scheme that efficiently identifies transient faults. The proposed circuit monitors transistors’ bulks of system’s blocks such as similar existing bulk built-in current sensor (BBICS) [5][6]. Our solution, though, is optimized to satisfy today’s need for low- power transient-fault robust systems. More precisely, to the best of our knowledge, the innovative contributions of this paper are: (1) an optimization of the original BBICS’s circuitry [5][6] to achieve reasonable overheads in power consumption; (2) the introduction of the sleep-mode for BBICS that allows additionally energy savings when the system is on standby; (3) a calibration method defined at design time for BBICS detecting a minimum profile of transient fault. II. BUILT-IN CURRENT SENSORS DETECTING TRANSIENT FAULTS Built-in current sensors (BICS) were initially proposed as a mechanism for detecting large increases in the current I DDQ consumed by a CMOS circuit during its quiescent state, i.e. when the circuit is not switching. The mechanism allows thus testing CMOS circuits against permanent faults [7]. Further, BICS were also adapted for detecting transient faults in memory cells (i.e. bit-flips) [8][9][10][11]. Recently, efforts were made for monitoring transient faults in combinational logic as well [12]. All these techniques connect BICS to the power lines (V DD and GND) of the monitored circuit in order to distinguish anomalous transient currents from normal currents. The today’s problem is that the amplitude of transient currents induced by radiation effects or fault attacks can have the same order of currents normally generated by switching activities in combinational logic circuits. Hence, schemes monitoring power lines are very limited for detecting just small range of transient faults. On the other hand, BICS connected to the bulks of the lirmm-00715126, version 1 - 6 Jul 2012 Author manuscript, published in "Colloque national du Groupement de Recherche System-On-Chip et System-In-Package France"