1 A new TPG structure for Datapath cores D. Berthelot, M.L. Flottes, B. Rouzeyre, Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier, U.M. CNRS 9928161 rue Ada, 34392 Montpellier Cedex 5, France berthelot@lirmm.fr, flottes@lirmm.fr, rouzeyre@lirmm.fr. Tel: (33) 4.67.41.85.27 Fax: (33) 4.67.41.85.00. Abstract The BIST approach discussed in this paper is based on the modification of pre-existing registers to perform test pattern generation (TPG). We present a new TPG structure particularly well-suited for datapath like cores. Generated test sequences are short and lead to high fault coverage for the most common modules in a datapath. We compare the proposed TPG with related structures. 1. Introduction BIST advantages are well known, it allows production testing as well as maintenance testing, it doesn’t need expensive Automatic Test Equipment and allows at speed testing. Per contra, BIST involves additional cost in terms of extra hardware for test pattern generation (TPG) and signature analysis (SA). Consequently, a BIST implementation is evaluated in terms of area overhead, achievable fault- coverage and test length resulting from the generated test sequence. These characteristics depend on the targeted test approach. In pseudo-random testing for example, test sequences can be easily generated by transforming pre-existing registers into Linear Feedback Shift Registers (LFSRs). Resulting test pattern generators do not need large additional area but long test sequences may be necessary to achieve high fault coverage. Pre-existing registers are also transformed into LFSRs to perform SA, the probability of aliasing in this case is closed to 1/2 n , where n is the number of stage in the LFSR. Recently, the Arithmetic BIST (ABIST) strategy [Gup94, Raj93] has been proposed for datapath like structures. Many datapaths modules (ALU, adders, multipliers, ...) are structurally regular and, due to this regularity, they can be tested very efficiently using short pseudo-exhaustive test sequences. Furthermore, these sequences can be generated using an adder-accumulator which is a common component in a datapath. The area overhead is all the more low as there is a sufficient number of pre-existing adder- accumulators in the datapath and as pre-existing wires connect these test pattern generators to other datapath components. A n-bits adder-accumulator used for SA leads to a probability of aliasing closed to 1/(2 n -1). We propose here a new structure for TPG in datapath like structures. Since the proposed test pattern generators are based on modification of pre- existing registers, TPG is easy to implement in any kind of datapaths. As in ABIST, the test approach is pseudo-exhaustive. We assume that SA is performed using LFSRs or adder-accumulators. 2. Preliminaries A typical datapath core is depicted in Figure 1. Datapaths are mainly composed of modules such as adders, multipliers, registers, multiplexors, .... Most of these modules are regular (ILA) i.e. they are built up as an interconnection of identical basic cells (e.g. the 2-bit full-adder cell is the basic cell of an n-bit adder). ROM RAM + * ALU R1 R2 R3 R4 R6 R5 Figure 1 : Datapath architecture A Cell Fault Model (CFM) has been proposed for such regular structures [Kau67], [Deb96]. This model is particularly well suited since it allows to model any combinational error occurring in a basic cell independently of its internal implementation. The CFM test of a module consists in exercising every single basic cell with an exhaustive test sequence, and in observing the cell responses through the module outputs. Note that the CFM includes the single stuck- at fault model (SSF), or in other words, that a complete test for CFM is also complete for SSF.