InAsSb and InGaAs linear and focal-plane arrays p. Merken', L. Zimmermann, J. John, S. Németh, M. Gastal, G. Borghs, C. Van Hoof IMEC, Kapeidreef 75, B-3001 Leuven, Belgium aA1SO at: Royal Military Academy, Brussels, Belgium ABSTRACT Short-wave JR and mid-JR photovoltaic detector arrays consisting of In(Ga)As and JnAsSb were realized. Maximum array size is 256x256 elements on a 25 micron pitch. The layers were grown on 3" semi-insulating GaAs substrates by MBE thereby avoiding the need for substrate removal by wafer thinning after hybridisation. A reliable and uniform detector process using improved wet-etching has been developed. The citric-acid based etch has been optimized for minimum underetch such that high fill factor is achieved even with a mesa-type process. Typical R0A products at room temperature are within a factor of 2 of the theoretical limit for bulk leakage currents. The hybridisation with silicon readout circuits consisted of Si-postprocessing by electroless plating or lithographic definition of Ni/Au, indium bump electroplating on the 111-v chip and flip-chip integration with individual indium bumps. The indium bump process resulted in 13 micron diameter solderbumps which allows pixel pitches below 20 micron. Keywords: JR detection, hybrid detectors, narrow-bandgap material, process technology 1. INTRODUCTION Although many material systems can be used to make infrared (JR) photovoltaic or photoconductive detector arrays, epitaxial growth and processing on large inexpensive substrates is the key to reduced cost of the sensor. At present only GaAs is a candidate since 6" substrates are readily available. Most research has however been devoted to epitaxial growth of extended InGaAs detectors on JnP [1,2] or InAsSb detectors on JnAs substrates [3] due to the reduced lattice mismatch. Growth of infrared detectors on GaAs, on GaAs-coated Si, or on patterned substrates [4-6] concentrates on reducing the defect levels compatible with uniform and large-scale array fabrication and in this article our results of heteroepitaxial JnGaAs, JnAs and InAsSb detector material grown on 3" GaAs substrates will be presented. The paper is organized as follows. First the structural aspects of JnGaAs and JnAsSb detector material is discussed. Then, the process development of the hybrid diode array process by means of wet chemical etching will be described. Finally, flip-chip process using Jndium plating process and the postprocessing of the silicon read-out electronics will be presented. 2. DETECTOR FABRICATION InGa1As and JnAs Sb p+ I p / n / n+ diodes are grown on 3" GaAs substrates by Molecular Beam Epitaxy (MBE). The details of the growth have been described elsewhere. Apart from inspection of the surface morphology and X-ray diffraction to determine the alloy compositions, the dislocation density is the most crucial parameter. Dislocations provide a leakage path and thereby deteriorate device performance, but furthermore assist diffusion (e.g. during processing) and thereby decrease both process and device reliability. Although transmission electron microscopy (TEM) is well suited to study the dislocation formation and annihilation process in a buffer layer, the absence of dislocations in a typical TEM cross-section can still imply a dislocation density of iO cm2 because of the limited investigated cross-section. As a more sensitive means to determine the dislocation density, we used an anisotropic etch to create etch-pits where dislocations are present (so-called 'dressing' of the dislocations). This approach has been used to investigate growth of low-Indium JnGaAs alloys on GaAs [7-8]. The device wafers were etched for 30 seconds in a AgNO3 containing HF:HNO3:H20 after which the etch visualized the dislocations. * Correspondence: E-mail: chris.vanhoof@imec.be; WWW: http://imec.be; Telephone: 32 16 281815; Fax: 32 16 281501 In Infrared Detectors and Focal Plane Arrays VI, Eustace L. Dereniak, Robert E. Sampson, Editors, 246 Proceedings of SPIE Vol. 4028 (2000) • 0277-786X!0O/$1 5.00