IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 12, DECEMBER 2011 2745 A 2.9–4.0-GHz Fractional-N Digital PLL Wit Bang-Bang Phase Detector and 560- fs rms Integrated Jitter at 4.5-mW Power Davide Tasca, Marco Zanuso, Member, IEEE, Giovanni Marzin, Salvatore Levantino, Member, IEEE, Carlo Samori, Senior Member, IEEE, and Andrea L. Lacaita, Fellow, IEEE Abstract—This paper introduces a 16 fractional-N digital PLL based on a single-bit TDC. A digital-to-time converter, placed in the feedback path, cancels out the quantization noise introduced by the dithering of the frequency divider modulus and permits to achieve low noise at low power. The PLL is implemented in a stan- dard 65-nm CMOS process. It achieves 102-dBc/Hz phase noise at 50-kHz offset and a total absolute jitter below 560 fs rms (inte- grated from 3 kHz to 30 MHz), even in the worst-case of a 42-dBc in-band fractional spur. The synthesizer tuning range spans from 2.92 GHz to 4.05 GHz with 70-Hz resolution. The total power con- sumption is 4.5 mW, which leads to the best jitter-power trade-off obtained with a fractional-N synthesizer. The synthesizer demon- strates the capability of frequency modulation up to 1.25-Mb/s data rate. Index Terms—ADPLL, bang-bang, DCO,DPLL,fractional-N, frequency synthesis, jitter,lead-lag, phasenoise,spur,TDC, TDC-less. I. I NTRODUCTION T HE advent of ultra-scaled CMOS technologies is leading to the digitalimplementation of criticalsubsystems, which traditionally belonged to the realm of analog circuits. This process is sustained by CMOS device scaling which offers both high-performance digital signal processing at very low costand better device matching for non-minimum-size devices. As an example, the trade-offs among resolution, con- version rate and power dissipation in analog-to-digital [1] and digital-to-analog converters (ADCs and DACs) improve with device scaling. Digitization not only entails the clear advantages of repeatability and portability to new scaled processes, but it also paves the way to the extensive application of powerful techniques for correcting the variable analog impairments. The frequency synthesizer, conventionally used for coherent demodulation/modulation in wireless transceivers, is one of the building blocks most involved in this evolution. A wealth of Manuscript received April 08, 2011; revised June 16, 2011; accepted July 15, 2011. Date of publication August 30, 2011; date of current version November 23, 2011. This paper was approved by Guest Editor Jafar Savoj. D. Tasca, G. Marzin, S. Levantino, C. Samori and A.L. Lacaita are with the Dipartimento di Elettronica e Informazione, Politecnico di Milano, Milan 20133, Italy (e-mail: levantin@elet.polimi.it). M. Zanuso was with the Dipartimento di Elettronica e Informazione, Po- litecnico di Milano, Milan,Italy,and is now with the Electrical Engineering Department, University of California, Los Angeles, CA 90095 USA (e-mail: zanuso@ee.ucla.edu). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/JSSC.2011.2162917 literature has been devoted to this topic, since the first digital phase-locked loop (PLL) for those applications was presen [2], less than one decade ago. The interest in this class of c is expected to increase with the introduction of fourth-gen tion high-data-rate communication standards, in particular or WiMAX, that require wideband radios with high signal-t noise ratio and may demand a local oscillator with integra noise lower than35 dB.This requirement is sometimes ex- pressed by means of the absolute jitter that is, roughly spe the RMS value of the difference between the zero-crossing stants of the PLL output with respect to an ideal noiseless 1 As an example, at 3.6 GHz the specification of integral noi than 35 dB translates into a jitter lower than 790 . This stringent requirement poses limitations to both tolerable p noise and spurs level. The improvement of noise and spurs formance always costs an increase in power dissipation; th fore, an important challenge is designing a high-efficiency quency synthesizer, which in other words has low jitter at power. A figure-of-merit (FoM), which can characterize a f quency synthesizer in terms of this jitter-power trade-off, has been introduced in [3], as the product of the jitter variance and the power consumption P expressed in milliwatts. State-of-the-art analog and digital fractional-N synthesiz are limited to a FoM of about 233 dB.This value becomes higher when in-band fractional spurs are taken into accoun comparing those values to the best FoM of 251 dB obtained in [3] for an integer-N synthesizer, we can realize how large efficiency gap still existing between integer- and fractiona synthesizers. The main goal of the present work is to reduce this gap and to design a fractional-N digital synthesizer wi FoM closer to the one of the best integer-N synthesizer, bu finer frequency resolution (below 100 Hz) and with wideba frequency modulation capability. The latter feature is esse for transmitters employing direct frequency modulation su the polar architecture. A digital PLL can be directly derived from the frac- tional-N analog PLL and the resulting simplified schematic sometimes referred asfractional-N digital PLL, is shown 1 This figure should not be confused with the period (or cycle) jitter, wh measures the RMS value of the stochastic process T[k] representing the tween the current period and the period of an ideal clock. If t[k] is the di between the real and ideal kth zero-crossing instant, it is T[k] = t[k]0t[k01] . 0018-9200/$26.00 © 2011 IEEE